1 /* 2 * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ZYNQMP_DEF_H 8 #define ZYNQMP_DEF_H 9 10 #include <plat/arm/common/smccc_def.h> 11 #include <plat/common/common_def.h> 12 13 #define ZYNQMP_CONSOLE_ID_cadence 1 14 #define ZYNQMP_CONSOLE_ID_cadence0 1 15 #define ZYNQMP_CONSOLE_ID_cadence1 2 16 #define ZYNQMP_CONSOLE_ID_dcc 3 17 #define ZYNQMP_CONSOLE_ID_dtb 4 18 19 #define CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE) 20 21 /* Runtime console */ 22 #define RT_CONSOLE_ID_cadence 1 23 #define RT_CONSOLE_ID_cadence0 1 24 #define RT_CONSOLE_ID_cadence1 2 25 #define RT_CONSOLE_ID_dcc 3 26 #define RT_CONSOLE_ID_dtb 4 27 28 #define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME) 29 30 /* Default counter frequency */ 31 #define ZYNQMP_DEFAULT_COUNTER_FREQ 0U 32 33 /* Firmware Image Package */ 34 #define ZYNQMP_PRIMARY_CPU 0 35 36 /* Memory location options for Shared data and TSP in ZYNQMP */ 37 #define ZYNQMP_IN_TRUSTED_SRAM 0 38 #define ZYNQMP_IN_TRUSTED_DRAM 1 39 40 /******************************************************************************* 41 * ZYNQMP memory map related constants 42 ******************************************************************************/ 43 /* Aggregate of all devices in the first GB */ 44 #define DEVICE0_BASE U(0xFF000000) 45 #define DEVICE0_SIZE U(0x00E00000) 46 #define DEVICE1_BASE U(0xF9000000) 47 #define DEVICE1_SIZE U(0x00800000) 48 49 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 50 #define CRF_APB_BASE U(0xFD1A0000) 51 #define CRF_APB_SIZE U(0x00600000) 52 #define CRF_APB_CLK_BASE U(0xFD1A0020) 53 54 /* CRF registers and bitfields */ 55 #define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104) 56 57 #define CRF_APB_RST_FPD_APU_ACPU_RESET (U(1) << 0) 58 #define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (U(1) << 10) 59 60 /* CRL registers and bitfields */ 61 #define CRL_APB_BASE U(0xFF5E0000) 62 #define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200) 63 #define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218) 64 #define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C) 65 #define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250)) 66 #define CRL_APB_CLK_BASE U(0xFF5E0020) 67 68 #define CRL_APB_RPU_AMBA_RESET (U(1) << 2) 69 #define CRL_APB_RPLL_CTRL_BYPASS (U(1) << 3) 70 71 #define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4) 72 73 #define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0) 74 #define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0) 75 #define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9) 76 #define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1) 77 #define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << \ 78 CRL_APB_BOOT_ENABLE_PIN_1_SHIFT) 79 #define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << \ 80 CRL_APB_BOOT_DRIVE_PIN_1_SHIFT) 81 #define ZYNQMP_BOOTMODE_JTAG U(0) 82 #define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | \ 83 CRL_APB_BOOT_DRIVE_PIN_1) 84 #define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1 85 86 /* system counter registers and bitfields */ 87 #define IOU_SCNTRS_BASE U(0xFF260000) 88 #define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20) 89 90 /* APU registers and bitfields */ 91 #define APU_BASE U(0xFD5C0000) 92 #define APU_CONFIG_0 (APU_BASE + 0x20) 93 #define APU_RVBAR_L_0 (APU_BASE + 0x40) 94 #define APU_RVBAR_H_0 (APU_BASE + 0x44) 95 #define APU_PWRCTL (APU_BASE + 0x90) 96 97 #define APU_CONFIG_0_VINITHI_SHIFT 8 98 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 99 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 100 #define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4 101 #define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8 102 103 /* PMU registers and bitfields */ 104 #define PMU_GLOBAL_BASE U(0xFFD80000) 105 #define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0) 106 #define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48) 107 #define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110) 108 #define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118) 109 #define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c) 110 #define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120) 111 112 #define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4) 113 114 /******************************************************************************* 115 * CCI-400 related constants 116 ******************************************************************************/ 117 #define PLAT_ARM_CCI_BASE U(0xFD6E0000) 118 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 119 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 120 121 /******************************************************************************* 122 * GIC-400 & interrupt handling related constants 123 ******************************************************************************/ 124 #define BASE_GICD_BASE U(0xF9010000) 125 #define BASE_GICC_BASE U(0xF9020000) 126 #define BASE_GICH_BASE U(0xF9040000) 127 #define BASE_GICV_BASE U(0xF9060000) 128 129 #if ZYNQMP_WDT_RESTART 130 #define IRQ_SEC_IPI_APU 67 131 #define IRQ_TTC3_1 77 132 #define TTC3_BASE_ADDR U(0xFF140000) 133 #define TTC3_INTR_REGISTER_1 (TTC3_BASE_ADDR + 0x54) 134 #define TTC3_INTR_ENABLE_1 (TTC3_BASE_ADDR + 0x60) 135 #endif 136 137 #define ARM_IRQ_SEC_PHY_TIMER 29 138 139 #define ARM_IRQ_SEC_SGI_0 8 140 #define ARM_IRQ_SEC_SGI_1 9 141 #define ARM_IRQ_SEC_SGI_2 10 142 #define ARM_IRQ_SEC_SGI_3 11 143 #define ARM_IRQ_SEC_SGI_4 12 144 #define ARM_IRQ_SEC_SGI_5 13 145 #define ARM_IRQ_SEC_SGI_6 14 146 #define ARM_IRQ_SEC_SGI_7 15 147 148 /* number of interrupt handlers. increase as required */ 149 #define MAX_INTR_EL3 2 150 151 /******************************************************************************* 152 * UART related constants 153 ******************************************************************************/ 154 #define ZYNQMP_UART0_BASE U(0xFF000000) 155 #define ZYNQMP_UART1_BASE U(0xFF010000) 156 157 /* Boot console */ 158 #if CONSOLE_IS(cadence) || CONSOLE_IS(dcc) || CONSOLE_IS(dtb) 159 # define UART_BASE ZYNQMP_UART0_BASE 160 #elif CONSOLE_IS(cadence1) 161 # define UART_BASE ZYNQMP_UART1_BASE 162 #else 163 # error "invalid ZYNQMP_CONSOLE" 164 #endif 165 166 /* Runtime console */ 167 #if defined(CONSOLE_RUNTIME) 168 #if RT_CONSOLE_IS(cadence) || RT_CONSOLE_IS(dcc) || RT_CONSOLE_IS(dtb) 169 # define RT_UART_BASE ZYNQMP_UART0_BASE 170 #elif RT_CONSOLE_IS(cadence1) 171 # define RT_UART_BASE ZYNQMP_UART1_BASE 172 #else 173 # error "invalid CONSOLE_RUNTIME" 174 #endif 175 #endif 176 177 /* Must be non zero */ 178 #define UART_BAUDRATE 115200 179 180 /* Silicon version detection */ 181 #define ZYNQMP_SILICON_VER_MASK 0xF000 182 #define ZYNQMP_SILICON_VER_SHIFT 12 183 #define ZYNQMP_CSU_VERSION_SILICON 0 184 #define ZYNQMP_CSU_VERSION_QEMU 3 185 186 #define ZYNQMP_RTL_VER_MASK 0xFF0U 187 #define ZYNQMP_RTL_VER_SHIFT 4 188 189 #define ZYNQMP_PS_VER_MASK 0xFU 190 #define ZYNQMP_PS_VER_SHIFT 0 191 192 #define ZYNQMP_CSU_BASEADDR U(0xFFCA0000) 193 #define ZYNQMP_CSU_IDCODE_OFFSET 0x40U 194 195 #define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0U 196 #define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFFU << \ 197 ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT) 198 #define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093 199 200 #define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12U 201 #define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7U << \ 202 ZYNQMP_CSU_IDCODE_SVD_SHIFT) 203 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15U 204 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xFU << \ 205 ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) 206 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19U 207 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3U << \ 208 ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT) 209 #define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21U 210 #define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7FU << \ 211 ZYNQMP_CSU_IDCODE_FAMILY_SHIFT) 212 #define ZYNQMP_CSU_IDCODE_FAMILY 0x23 213 214 #define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28U 215 #define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xFU << \ 216 ZYNQMP_CSU_IDCODE_REVISION_SHIFT) 217 #define ZYNQMP_CSU_IDCODE_REVISION 0U 218 219 #define ZYNQMP_CSU_VERSION_OFFSET 0x44U 220 221 /* Efuse */ 222 #define EFUSE_BASEADDR U(0xFFCC0000) 223 #define EFUSE_IPDISABLE_OFFSET 0x1018 224 #define EFUSE_IPDISABLE_VERSION 0x1FFU 225 #define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20 226 227 /* Access control register defines */ 228 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 229 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 230 231 #define FPD_SLCR_BASEADDR U(0xFD610000) 232 #define IOU_SLCR_BASEADDR U(0xFF180000) 233 234 #define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000) 235 #define ZYNQMP_RPU0_CFG U(0xFF9A0100) 236 #define ZYNQMP_RPU1_CFG U(0xFF9A0200) 237 #define ZYNQMP_SLSPLIT_MASK U(0x08) 238 #define ZYNQMP_TCM_COMB_MASK U(0x40) 239 #define ZYNQMP_SLCLAMP_MASK U(0x10) 240 #define ZYNQMP_VINITHI_MASK U(0x04) 241 242 /* Tap delay bypass */ 243 #define IOU_TAPDLY_BYPASS U(0XFF180390) 244 #define TAP_DELAY_MASK U(0x7) 245 246 /* SD DLL reset */ 247 #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) 248 #define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004) 249 #define ZYNQMP_SD0_DLL_RST U(0x00000004) 250 #define ZYNQMP_SD1_DLL_RST_MASK U(0x00040000) 251 #define ZYNQMP_SD1_DLL_RST U(0x00040000) 252 253 /* SD tap delay */ 254 #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) 255 #define ZYNQMP_SD_ITAP_DLY U(0xFF180314) 256 #define ZYNQMP_SD_OTAP_DLY U(0xFF180318) 257 #define ZYNQMP_SD_TAP_OFFSET U(16) 258 #define ZYNQMP_SD_ITAPCHGWIN_MASK U(0x200) 259 #define ZYNQMP_SD_ITAPCHGWIN U(0x200) 260 #define ZYNQMP_SD_ITAPDLYENA_MASK U(0x100) 261 #define ZYNQMP_SD_ITAPDLYENA U(0x100) 262 #define ZYNQMP_SD_ITAPDLYSEL_MASK U(0xFF) 263 #define ZYNQMP_SD_OTAPDLYSEL_MASK U(0x3F) 264 #define ZYNQMP_SD_OTAPDLYENA_MASK U(0x40) 265 #define ZYNQMP_SD_OTAPDLYENA U(0x40) 266 267 /* Clock control registers */ 268 /* Full power domain clocks */ 269 #define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00) 270 #define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c) 271 #define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18) 272 #define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24) 273 #define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28) 274 #define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c) 275 #define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30) 276 /* Peripheral clocks */ 277 #define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40) 278 #define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44) 279 #define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48) 280 #define CRF_APB_DP_VIDEO_REF_CTRL (CRF_APB_CLK_BASE + 0x50) 281 #define CRF_APB_DP_AUDIO_REF_CTRL (CRF_APB_CLK_BASE + 0x54) 282 #define CRF_APB_DP_STC_REF_CTRL (CRF_APB_CLK_BASE + 0x5c) 283 #define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60) 284 #define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64) 285 #define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80) 286 #define CRF_APB_PCIE_REF_CTRL (CRF_APB_CLK_BASE + 0x94) 287 #define CRF_APB_GDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x98) 288 #define CRF_APB_DPDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x9c) 289 #define CRF_APB_TOPSW_MAIN_CTRL (CRF_APB_CLK_BASE + 0xa0) 290 #define CRF_APB_TOPSW_LSBUS_CTRL (CRF_APB_CLK_BASE + 0xa4) 291 #define CRF_APB_GTGREF0_REF_CTRL (CRF_APB_CLK_BASE + 0xa8) 292 #define CRF_APB_DBG_TSTMP_CTRL (CRF_APB_CLK_BASE + 0xd8) 293 294 /* Low power domain clocks */ 295 #define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00) 296 #define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10) 297 #define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20) 298 #define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24) 299 #define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28) 300 /* Peripheral clocks */ 301 #define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c) 302 #define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30) 303 #define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34) 304 #define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38) 305 #define CRL_APB_GEM3_REF_CTRL (CRL_APB_CLK_BASE + 0x3c) 306 #define CRL_APB_USB0_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x40) 307 #define CRL_APB_USB1_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x44) 308 #define CRL_APB_QSPI_REF_CTRL (CRL_APB_CLK_BASE + 0x48) 309 #define CRL_APB_SDIO0_REF_CTRL (CRL_APB_CLK_BASE + 0x4c) 310 #define CRL_APB_SDIO1_REF_CTRL (CRL_APB_CLK_BASE + 0x50) 311 #define CRL_APB_UART0_REF_CTRL (CRL_APB_CLK_BASE + 0x54) 312 #define CRL_APB_UART1_REF_CTRL (CRL_APB_CLK_BASE + 0x58) 313 #define CRL_APB_SPI0_REF_CTRL (CRL_APB_CLK_BASE + 0x5c) 314 #define CRL_APB_SPI1_REF_CTRL (CRL_APB_CLK_BASE + 0x60) 315 #define CRL_APB_CAN0_REF_CTRL (CRL_APB_CLK_BASE + 0x64) 316 #define CRL_APB_CAN1_REF_CTRL (CRL_APB_CLK_BASE + 0x68) 317 #define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70) 318 #define CRL_APB_IOU_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x7c) 319 #define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80) 320 #define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84) 321 #define CRL_APB_LPD_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x88) 322 #define CRL_APB_LPD_LSBUS_CTRL (CRL_APB_CLK_BASE + 0x8c) 323 #define CRL_APB_DBG_LPD_CTRL (CRL_APB_CLK_BASE + 0x90) 324 #define CRL_APB_NAND_REF_CTRL (CRL_APB_CLK_BASE + 0x94) 325 #define CRL_APB_ADMA_REF_CTRL (CRL_APB_CLK_BASE + 0x98) 326 #define CRL_APB_PL0_REF_CTRL (CRL_APB_CLK_BASE + 0xa0) 327 #define CRL_APB_PL1_REF_CTRL (CRL_APB_CLK_BASE + 0xa4) 328 #define CRL_APB_PL2_REF_CTRL (CRL_APB_CLK_BASE + 0xa8) 329 #define CRL_APB_PL3_REF_CTRL (CRL_APB_CLK_BASE + 0xac) 330 #define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4) 331 #define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc) 332 #define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4) 333 #define CRL_APB_PL3_THR_CNT (CRL_APB_CLK_BASE + 0xdc) 334 #define CRL_APB_GEM_TSU_REF_CTRL (CRL_APB_CLK_BASE + 0xe0) 335 #define CRL_APB_DLL_REF_CTRL (CRL_APB_CLK_BASE + 0xe4) 336 #define CRL_APB_AMS_REF_CTRL (CRL_APB_CLK_BASE + 0xe8) 337 #define CRL_APB_I2C0_REF_CTRL (CRL_APB_CLK_BASE + 0x100) 338 #define CRL_APB_I2C1_REF_CTRL (CRL_APB_CLK_BASE + 0x104) 339 #define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108) 340 #define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308) 341 #define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304) 342 #define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100) 343 #define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300) 344 345 /* Global general storage register base address */ 346 #define GGS_BASEADDR (0xFFD80030U) 347 #define GGS_NUM_REGS U(4) 348 349 /* Persistent global general storage register base address */ 350 #define PGGS_BASEADDR (0xFFD80050U) 351 #define PGGS_NUM_REGS U(4) 352 353 /* PMU GGS4 register 4 is used for warm restart boot health status */ 354 #define PMU_GLOBAL_GEN_STORAGE4 (GGS_BASEADDR + 0x10) 355 /* Warm restart boot health status mask */ 356 #define PM_BOOT_HEALTH_STATUS_MASK U(0x01) 357 /* WDT restart scope shift and mask */ 358 #define RESTART_SCOPE_SHIFT (3) 359 #define RESTART_SCOPE_MASK (0x3U << RESTART_SCOPE_SHIFT) 360 361 /* AFI registers */ 362 #define AFIFM6_WRCTRL U(13) 363 #define FABRIC_WIDTH U(3) 364 365 /* CSUDMA Module Base Address*/ 366 #define CSUDMA_BASE U(0xFFC80000) 367 368 /* RSA-CORE Module Base Address*/ 369 #define RSA_CORE_BASE U(0xFFCE0000) 370 371 #endif /* ZYNQMP_DEF_H */ 372