1 /* 2 * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include <common/interrupt_props.h> 14 #include <drivers/arm/gic_common.h> 15 #include <lib/utils_def.h> 16 17 #include "zynqmp_def.h" 18 19 /******************************************************************************* 20 * Generic platform constants 21 ******************************************************************************/ 22 23 /* Size of cacheable stacks */ 24 #ifndef PLATFORM_STACK_SIZE 25 #define PLATFORM_STACK_SIZE 0x440 26 #endif 27 28 #define PLATFORM_CORE_COUNT U(4) 29 #define PLAT_NUM_POWER_DOMAINS U(5) 30 #define PLAT_MAX_PWR_LVL U(1) 31 #define PLAT_MAX_RET_STATE U(1) 32 #define PLAT_MAX_OFF_STATE U(2) 33 34 /******************************************************************************* 35 * BL31 specific defines. 36 ******************************************************************************/ 37 /* 38 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 39 * present). BL31_BASE is calculated using the current BL31 debug size plus a 40 * little space for growth. 41 */ 42 #ifndef ZYNQMP_ATF_MEM_BASE 43 #if !DEBUG && defined(SPD_none) && !SDEI_SUPPORT 44 # define BL31_BASE U(0xfffea000) 45 # define BL31_LIMIT U(0x100000000) 46 #else 47 # define BL31_BASE U(0x1000) 48 # define BL31_LIMIT U(0x7ffff) 49 #endif 50 #else 51 # define BL31_BASE (ZYNQMP_ATF_MEM_BASE) 52 # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1) 53 # ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE 54 # define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1) 55 # endif 56 #endif 57 58 /******************************************************************************* 59 * BL32 specific defines. 60 ******************************************************************************/ 61 #ifndef ZYNQMP_BL32_MEM_BASE 62 # define BL32_BASE U(0x60000000) 63 # define BL32_LIMIT U(0x7fffffff) 64 #else 65 # define BL32_BASE (ZYNQMP_BL32_MEM_BASE) 66 # define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1) 67 #endif 68 69 /******************************************************************************* 70 * BL33 specific defines. 71 ******************************************************************************/ 72 #ifndef PRELOADED_BL33_BASE 73 # define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) 74 #else 75 # define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE 76 #endif 77 78 /******************************************************************************* 79 * TSP specific defines. 80 ******************************************************************************/ 81 #define TSP_SEC_MEM_BASE BL32_BASE 82 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 83 84 /* ID of the secure physical generic timer interrupt used by the TSP */ 85 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 86 87 /******************************************************************************* 88 * Platform specific page table and MMU setup constants 89 ******************************************************************************/ 90 #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) 91 #define PLAT_DDR_LOWMEM_MAX U(0x80000000) 92 #define PLAT_OCM_BASE U(0xFFFC0000) 93 #define PLAT_OCM_LIMIT U(0xFFFFFFFF) 94 95 #define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) 96 97 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 98 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 99 100 #ifndef MAX_MMAP_REGIONS 101 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 102 #define MAX_MMAP_REGIONS 8 103 #else 104 #define MAX_MMAP_REGIONS 7 105 #endif 106 #endif 107 108 #ifndef MAX_XLAT_TABLES 109 #if !IS_TFA_IN_OCM(BL31_BASE) 110 #define MAX_XLAT_TABLES 8 111 #else 112 #define MAX_XLAT_TABLES 5 113 #endif 114 #endif 115 116 #define CACHE_WRITEBACK_SHIFT 6 117 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 118 119 #define ZYNQMP_SDEI_SGI_PRIVATE U(8) 120 121 /* Platform macros to support exception handling framework */ 122 #define PLAT_PRI_BITS U(3) 123 #define PLAT_SDEI_CRITICAL_PRI 0x10 124 #define PLAT_SDEI_NORMAL_PRI 0x20 125 126 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 127 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 128 /* 129 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 130 * terminology. On a GICv2 system or mode, the lists will be merged and treated 131 * as Group 0 interrupts. 132 */ 133 #if !ZYNQMP_WDT_RESTART 134 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 135 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 136 GIC_INTR_CFG_LEVEL), \ 137 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 138 GIC_INTR_CFG_EDGE), \ 139 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 140 GIC_INTR_CFG_EDGE), \ 141 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 142 GIC_INTR_CFG_EDGE), \ 143 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 144 GIC_INTR_CFG_EDGE), \ 145 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 146 GIC_INTR_CFG_EDGE), \ 147 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 148 GIC_INTR_CFG_EDGE), \ 149 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 150 GIC_INTR_CFG_EDGE) 151 #else 152 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 153 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 154 GIC_INTR_CFG_LEVEL), \ 155 INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 156 GIC_INTR_CFG_EDGE), \ 157 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 158 GIC_INTR_CFG_EDGE), \ 159 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 160 GIC_INTR_CFG_EDGE), \ 161 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 162 GIC_INTR_CFG_EDGE), \ 163 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 164 GIC_INTR_CFG_EDGE), \ 165 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 166 GIC_INTR_CFG_EDGE), \ 167 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 168 GIC_INTR_CFG_EDGE), \ 169 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 170 GIC_INTR_CFG_EDGE) 171 #endif 172 173 #define PLAT_ARM_G0_IRQ_PROPS(grp) \ 174 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \ 175 GIC_INTR_CFG_EDGE) 176 177 #endif /* PLATFORM_DEF_H */ 178