131c3842eSJolly Shah /* 2*55a08b35SAmbroise Vincent * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 331c3842eSJolly Shah * 431c3842eSJolly Shah * SPDX-License-Identifier: BSD-3-Clause 531c3842eSJolly Shah */ 631c3842eSJolly Shah 731c3842eSJolly Shah #ifndef PLAT_PRIVATE_H 831c3842eSJolly Shah #define PLAT_PRIVATE_H 931c3842eSJolly Shah 1031c3842eSJolly Shah #include <stdint.h> 1131c3842eSJolly Shah 1231c3842eSJolly Shah #include <bl31/interrupt_mgmt.h> 1331c3842eSJolly Shah #include <common/bl_common.h> 14*55a08b35SAmbroise Vincent #include <drivers/cadence/cdns_uart.h> 1531c3842eSJolly Shah 1631c3842eSJolly Shah void zynqmp_config_setup(void); 1731c3842eSJolly Shah 1831c3842eSJolly Shah unsigned int zynqmp_calc_core_pos(u_register_t mpidr); 1931c3842eSJolly Shah 2031c3842eSJolly Shah /* ZynqMP specific functions */ 2131c3842eSJolly Shah unsigned int zynqmp_get_uart_clk(void); 2231c3842eSJolly Shah unsigned int zynqmp_get_bootmode(void); 2331c3842eSJolly Shah 2431c3842eSJolly Shah /* For FSBL handover */ 2531c3842eSJolly Shah enum fsbl_handoff { 2631c3842eSJolly Shah FSBL_HANDOFF_SUCCESS = 0, 2731c3842eSJolly Shah FSBL_HANDOFF_NO_STRUCT, 2831c3842eSJolly Shah FSBL_HANDOFF_INVAL_STRUCT, 2931c3842eSJolly Shah FSBL_HANDOFF_TOO_MANY_PARTS, 3031c3842eSJolly Shah }; 3131c3842eSJolly Shah 3231c3842eSJolly Shah #if ZYNQMP_WDT_RESTART 3331c3842eSJolly Shah /* 3431c3842eSJolly Shah * Register handler to specific GIC entrance 3531c3842eSJolly Shah * for INTR_TYPE_EL3 type of interrupt 3631c3842eSJolly Shah */ 3731c3842eSJolly Shah int request_intr_type_el3(uint32_t, interrupt_type_handler_t); 3831c3842eSJolly Shah #endif 3931c3842eSJolly Shah 4031c3842eSJolly Shah enum fsbl_handoff fsbl_atf_handover(entry_point_info_t *bl32_image_ep_info, 4131c3842eSJolly Shah entry_point_info_t *bl33_image_ep_info); 4231c3842eSJolly Shah 4331c3842eSJolly Shah #endif /* PLAT_PRIVATE_H */ 44