131c3842eSJolly Shah /* 2619bc13eSMichal Simek * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved. 3e8d61f7dSPrasad Kummari * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. 431c3842eSJolly Shah * 531c3842eSJolly Shah * SPDX-License-Identifier: BSD-3-Clause 631c3842eSJolly Shah */ 731c3842eSJolly Shah 831c3842eSJolly Shah #ifndef PLAT_PRIVATE_H 931c3842eSJolly Shah #define PLAT_PRIVATE_H 1031c3842eSJolly Shah 1131c3842eSJolly Shah #include <stdint.h> 1231c3842eSJolly Shah 1331c3842eSJolly Shah #include <bl31/interrupt_mgmt.h> 1431c3842eSJolly Shah #include <common/bl_common.h> 1555a08b35SAmbroise Vincent #include <drivers/cadence/cdns_uart.h> 1631c3842eSJolly Shah 1731c3842eSJolly Shah void zynqmp_config_setup(void); 1831c3842eSJolly Shah 19ffa91031SVenkatesh Yadav Abbarapu uint32_t zynqmp_calc_core_pos(u_register_t mpidr); 2031c3842eSJolly Shah 2131c3842eSJolly Shah /* ZynqMP specific functions */ 22*04a48335SMichal Simek uint32_t get_uart_clk(void); 23ffa91031SVenkatesh Yadav Abbarapu uint32_t zynqmp_get_bootmode(void); 2431c3842eSJolly Shah 2531c3842eSJolly Shah #if ZYNQMP_WDT_RESTART 26e8d61f7dSPrasad Kummari typedef struct zynqmp_intr_info_type_el3 { 27e8d61f7dSPrasad Kummari uint32_t id; 28e8d61f7dSPrasad Kummari interrupt_type_handler_t handler; 29e8d61f7dSPrasad Kummari } zynmp_intr_info_type_el3_t; 30e8d61f7dSPrasad Kummari 3131c3842eSJolly Shah /* 3231c3842eSJolly Shah * Register handler to specific GIC entrance 3331c3842eSJolly Shah * for INTR_TYPE_EL3 type of interrupt 3431c3842eSJolly Shah */ 3531c3842eSJolly Shah int request_intr_type_el3(uint32_t, interrupt_type_handler_t); 3631c3842eSJolly Shah #endif 3731c3842eSJolly Shah 3831c3842eSJolly Shah #endif /* PLAT_PRIVATE_H */ 39