1 /* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <bl31/bl31.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/arm/dcc.h> 14 #include <drivers/console.h> 15 #include <plat/arm/common/plat_arm.h> 16 #include <plat/common/platform.h> 17 #include <lib/mmio.h> 18 19 #include <plat_startup.h> 20 #include <plat_private.h> 21 #include <zynqmp_def.h> 22 23 static entry_point_info_t bl32_image_ep_info; 24 static entry_point_info_t bl33_image_ep_info; 25 26 /* 27 * Return a pointer to the 'entry_point_info' structure of the next image for 28 * the security state specified. BL33 corresponds to the non-secure image type 29 * while BL32 corresponds to the secure image type. A NULL pointer is returned 30 * if the image does not exist. 31 */ 32 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 33 { 34 assert(sec_state_is_valid(type)); 35 36 if (type == NON_SECURE) { 37 return &bl33_image_ep_info; 38 } 39 40 return &bl32_image_ep_info; 41 } 42 43 /* 44 * Set the build time defaults. We want to do this when doing a JTAG boot 45 * or if we can't find any other config data. 46 */ 47 static inline void bl31_set_default_config(void) 48 { 49 bl32_image_ep_info.pc = BL32_BASE; 50 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 51 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 52 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 53 DISABLE_ALL_EXCEPTIONS); 54 } 55 56 /* 57 * Perform any BL31 specific platform actions. Here is an opportunity to copy 58 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 59 * are lost (potentially). This needs to be done before the MMU is initialized 60 * so that the memory layout can be used while creating page tables. 61 */ 62 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 63 u_register_t arg2, u_register_t arg3) 64 { 65 uint64_t atf_handoff_addr; 66 67 if (ZYNQMP_CONSOLE_IS(cadence)) { 68 /* Register the console to provide early debug support */ 69 static console_t bl31_boot_console; 70 (void)console_cdns_register(ZYNQMP_UART_BASE, 71 zynqmp_get_uart_clk(), 72 ZYNQMP_UART_BAUDRATE, 73 &bl31_boot_console); 74 console_set_scope(&bl31_boot_console, 75 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT); 76 } else if (ZYNQMP_CONSOLE_IS(dcc)) { 77 /* Initialize the dcc console for debug */ 78 int rc = console_dcc_register(); 79 if (rc == 0) { 80 panic(); 81 } 82 } 83 /* Initialize the platform config for future decision making */ 84 zynqmp_config_setup(); 85 86 /* There are no parameters from BL2 if BL31 is a reset vector */ 87 assert(arg0 == 0U); 88 assert(arg1 == 0U); 89 90 /* 91 * Do initial security configuration to allow DRAM/device access. On 92 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but 93 * other platforms might have more programmable security devices 94 * present. 95 */ 96 97 /* Populate common information for BL32 and BL33 */ 98 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 99 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 100 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 101 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 102 103 atf_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); 104 105 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { 106 bl31_set_default_config(); 107 } else { 108 /* use parameters from FSBL */ 109 enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, 110 &bl33_image_ep_info, 111 atf_handoff_addr); 112 if (ret == FSBL_HANDOFF_NO_STRUCT) { 113 bl31_set_default_config(); 114 } else if (ret != FSBL_HANDOFF_SUCCESS) { 115 panic(); 116 } 117 } 118 if (bl32_image_ep_info.pc) { 119 VERBOSE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 120 } 121 if (bl33_image_ep_info.pc) { 122 VERBOSE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 123 } 124 } 125 126 /* Enable the test setup */ 127 #ifndef ZYNQMP_TESTING 128 static void zynqmp_testing_setup(void) { } 129 #else 130 static void zynqmp_testing_setup(void) 131 { 132 uint32_t actlr_el3, actlr_el2; 133 134 /* Enable CPU ACTLR AND L2ACTLR RW access from non-secure world */ 135 actlr_el3 = read_actlr_el3(); 136 actlr_el2 = read_actlr_el2(); 137 138 actlr_el3 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; 139 actlr_el2 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; 140 write_actlr_el3(actlr_el3); 141 write_actlr_el2(actlr_el2); 142 } 143 #endif 144 145 #if ZYNQMP_WDT_RESTART 146 static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3]; 147 148 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 149 { 150 /* Validate 'handler' and 'id' parameters */ 151 if (!handler || id >= MAX_INTR_EL3) { 152 return -EINVAL; 153 } 154 155 /* Check if a handler has already been registered */ 156 if (type_el3_interrupt_table[id]) { 157 return -EALREADY; 158 } 159 160 type_el3_interrupt_table[id] = handler; 161 162 return 0; 163 } 164 165 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 166 void *handle, void *cookie) 167 { 168 uint32_t intr_id; 169 interrupt_type_handler_t handler; 170 171 intr_id = plat_ic_get_pending_interrupt_id(); 172 handler = type_el3_interrupt_table[intr_id]; 173 if (handler != NULL) { 174 handler(intr_id, flags, handle, cookie); 175 } 176 177 return 0; 178 } 179 #endif 180 181 void bl31_platform_setup(void) 182 { 183 /* Initialize the gic cpu and distributor interfaces */ 184 plat_arm_gic_driver_init(); 185 plat_arm_gic_init(); 186 zynqmp_testing_setup(); 187 } 188 189 void bl31_plat_runtime_setup(void) 190 { 191 #if ZYNQMP_WDT_RESTART 192 uint64_t flags = 0; 193 uint64_t rc; 194 195 set_interrupt_rm_flag(flags, NON_SECURE); 196 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 197 rdo_el3_interrupt_handler, flags); 198 if (rc) { 199 panic(); 200 } 201 #endif 202 } 203 204 /* 205 * Perform the very early platform specific architectural setup here. 206 */ 207 void bl31_plat_arch_setup(void) 208 { 209 plat_arm_interconnect_init(); 210 plat_arm_interconnect_enter_coherency(); 211 212 213 const mmap_region_t bl_regions[] = { 214 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 215 MT_MEMORY | MT_RW | MT_SECURE), 216 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 217 MT_CODE | MT_SECURE), 218 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 219 MT_RO_DATA | MT_SECURE), 220 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 221 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 222 MT_DEVICE | MT_RW | MT_SECURE), 223 {0} 224 }; 225 226 setup_page_tables(bl_regions, plat_arm_get_mmap()); 227 enable_mmu_el3(0); 228 } 229