1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 11 #include <bl31/bl31.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/fdt_fixup.h> 15 #include <common/fdt_wrappers.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/mmio.h> 18 #include <lib/xlat_tables/xlat_tables_v2.h> 19 #include <libfdt.h> 20 #include <plat/arm/common/plat_arm.h> 21 #include <plat/common/platform.h> 22 #include <plat_console.h> 23 24 #include <custom_svc.h> 25 #include <plat_fdt.h> 26 #include <plat_private.h> 27 #include <plat_startup.h> 28 #include <zynqmp_def.h> 29 30 31 static entry_point_info_t bl32_image_ep_info; 32 static entry_point_info_t bl33_image_ep_info; 33 34 /* 35 * Return a pointer to the 'entry_point_info' structure of the next image for 36 * the security state specified. BL33 corresponds to the non-secure image type 37 * while BL32 corresponds to the secure image type. A NULL pointer is returned 38 * if the image does not exist. 39 */ 40 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 41 { 42 entry_point_info_t *next_image_info; 43 44 assert(sec_state_is_valid(type)); 45 if (type == NON_SECURE) { 46 next_image_info = &bl33_image_ep_info; 47 } else { 48 next_image_info = &bl32_image_ep_info; 49 } 50 51 return next_image_info; 52 } 53 54 /* 55 * Set the build time defaults. We want to do this when doing a JTAG boot 56 * or if we can't find any other config data. 57 */ 58 static inline void bl31_set_default_config(void) 59 { 60 bl32_image_ep_info.pc = BL32_BASE; 61 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 62 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 63 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 64 DISABLE_ALL_EXCEPTIONS); 65 } 66 67 static inline uint64_t read_cntvct_el0(void) 68 { 69 uint64_t val; 70 71 asm volatile("mrs %0, cntvct_el0" : "=r" (val)); 72 return val; 73 } 74 75 static inline void reset_cntvct_el0_to_zero(void) 76 { 77 asm volatile( 78 "mrs x0, cntpct_el0\n" /* Read physical counter into x0 */ 79 "neg x0, x0\n" /* Negate it: x0 = -x0 */ 80 "msr cntvoff_el2, x0\n" /* Write offset to virtual counter */ 81 : 82 : 83 : "x0", "memory" 84 ); 85 } 86 87 /* 88 * Perform any BL31 specific platform actions. Here is an opportunity to copy 89 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 90 * are lost (potentially). This needs to be done before the MMU is initialized 91 * so that the memory layout can be used while creating page tables. 92 */ 93 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 94 u_register_t arg2, u_register_t arg3) 95 { 96 (void)arg0; 97 (void)arg1; 98 (void)arg2; 99 (void)arg3; 100 uint64_t tfa_handoff_addr; 101 uint64_t counter_freq; 102 103 /* Configure counter frequency */ 104 counter_freq = read_cntfrq_el0(); 105 if (counter_freq == ZYNQMP_DEFAULT_COUNTER_FREQ) { 106 write_cntfrq_el0(plat_get_syscnt_freq2()); 107 } 108 109 generic_delay_timer_init(); 110 111 setup_console(); 112 113 /* Initialize the platform config for future decision making */ 114 zynqmp_config_setup(); 115 116 INFO("Counter TICK 0x%lx\n", read_cntvct_el0()); 117 reset_cntvct_el0_to_zero(); 118 INFO("Counter TICK after reset 0x%lx\n", read_cntvct_el0()); 119 120 /* 121 * Do initial security configuration to allow DRAM/device access. On 122 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but 123 * other platforms might have more programmable security devices 124 * present. 125 */ 126 127 /* Populate common information for BL32 and BL33 */ 128 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 129 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 130 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 131 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 132 133 tfa_handoff_addr = (uint64_t)mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); 134 135 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { 136 bl31_set_default_config(); 137 } else { 138 /* use parameters from XBL */ 139 enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info, 140 &bl33_image_ep_info, 141 tfa_handoff_addr); 142 if (ret != XBL_HANDOFF_SUCCESS) { 143 panic(); 144 } 145 } 146 if (bl32_image_ep_info.pc != 0U) { 147 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 148 } 149 if (bl33_image_ep_info.pc != 0U) { 150 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 151 } 152 153 custom_early_setup(); 154 155 } 156 157 #if ZYNQMP_WDT_RESTART 158 static zynmp_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 159 160 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 161 { 162 static uint32_t index; 163 uint32_t i; 164 165 /* Validate 'handler' and 'id' parameters */ 166 if (!handler || index >= MAX_INTR_EL3) { 167 return -EINVAL; 168 } 169 170 /* Check if a handler has already been registered */ 171 for (i = 0; i < index; i++) { 172 if (id == type_el3_interrupt_table[i].id) { 173 return -EALREADY; 174 } 175 } 176 177 type_el3_interrupt_table[index].id = id; 178 type_el3_interrupt_table[index].handler = handler; 179 180 index++; 181 182 return 0; 183 } 184 185 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 186 void *handle, void *cookie) 187 { 188 uint32_t intr_id; 189 uint32_t i; 190 interrupt_type_handler_t handler = NULL; 191 192 intr_id = plat_ic_get_pending_interrupt_id(); 193 194 for (i = 0; i < MAX_INTR_EL3; i++) { 195 if (intr_id == type_el3_interrupt_table[i].id) { 196 handler = type_el3_interrupt_table[i].handler; 197 } 198 } 199 200 if (handler != NULL) { 201 return handler(intr_id, flags, handle, cookie); 202 } 203 204 return 0; 205 } 206 #endif 207 208 void bl31_platform_setup(void) 209 { 210 prepare_dtb(); 211 212 /* Initialize the gic cpu and distributor interfaces */ 213 plat_arm_gic_driver_init(); 214 plat_arm_gic_init(); 215 } 216 217 void bl31_plat_runtime_setup(void) 218 { 219 #if ZYNQMP_WDT_RESTART 220 uint64_t flags = 0; 221 uint64_t rc; 222 223 set_interrupt_rm_flag(flags, NON_SECURE); 224 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 225 rdo_el3_interrupt_handler, flags); 226 if (rc) { 227 panic(); 228 } 229 #endif 230 231 custom_runtime_setup(); 232 } 233 234 /* 235 * Perform the very early platform specific architectural setup here. 236 */ 237 void bl31_plat_arch_setup(void) 238 { 239 plat_arm_interconnect_init(); 240 plat_arm_interconnect_enter_coherency(); 241 242 const mmap_region_t bl_regions[] = { 243 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 244 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 245 MT_MEMORY | MT_RW | MT_NS), 246 #endif 247 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 248 MT_MEMORY | MT_RW | MT_SECURE), 249 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 250 MT_CODE | MT_SECURE), 251 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 252 MT_RO_DATA | MT_SECURE), 253 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 254 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 255 MT_DEVICE | MT_RW | MT_SECURE), 256 {0} 257 }; 258 259 custom_mmap_add(); 260 261 setup_page_tables(bl_regions, plat_get_mmap()); 262 enable_mmu(0); 263 } 264