1 /* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <bl31/bl31.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/arm/dcc.h> 14 #include <drivers/console.h> 15 #include <plat/arm/common/plat_arm.h> 16 #include <plat/common/platform.h> 17 #include <lib/mmio.h> 18 19 #include <plat_startup.h> 20 #include <plat_private.h> 21 #include <zynqmp_def.h> 22 23 #include <common/fdt_fixup.h> 24 #include <common/fdt_wrappers.h> 25 #include <libfdt.h> 26 27 static entry_point_info_t bl32_image_ep_info; 28 static entry_point_info_t bl33_image_ep_info; 29 30 /* 31 * Return a pointer to the 'entry_point_info' structure of the next image for 32 * the security state specified. BL33 corresponds to the non-secure image type 33 * while BL32 corresponds to the secure image type. A NULL pointer is returned 34 * if the image does not exist. 35 */ 36 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 37 { 38 entry_point_info_t *next_image_info; 39 40 assert(sec_state_is_valid(type)); 41 if (type == NON_SECURE) { 42 next_image_info = &bl33_image_ep_info; 43 } else { 44 next_image_info = &bl32_image_ep_info; 45 } 46 47 return next_image_info; 48 } 49 50 /* 51 * Set the build time defaults. We want to do this when doing a JTAG boot 52 * or if we can't find any other config data. 53 */ 54 static inline void bl31_set_default_config(void) 55 { 56 bl32_image_ep_info.pc = BL32_BASE; 57 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 58 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 59 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 60 DISABLE_ALL_EXCEPTIONS); 61 } 62 63 /* 64 * Perform any BL31 specific platform actions. Here is an opportunity to copy 65 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 66 * are lost (potentially). This needs to be done before the MMU is initialized 67 * so that the memory layout can be used while creating page tables. 68 */ 69 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 70 u_register_t arg2, u_register_t arg3) 71 { 72 uint64_t atf_handoff_addr; 73 74 if (ZYNQMP_CONSOLE_IS(cadence) || (ZYNQMP_CONSOLE_IS(cadence1))) { 75 /* Register the console to provide early debug support */ 76 static console_t bl31_boot_console; 77 (void)console_cdns_register(ZYNQMP_UART_BASE, 78 zynqmp_get_uart_clk(), 79 ZYNQMP_UART_BAUDRATE, 80 &bl31_boot_console); 81 console_set_scope(&bl31_boot_console, 82 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT); 83 } else if (ZYNQMP_CONSOLE_IS(dcc)) { 84 /* Initialize the dcc console for debug */ 85 int32_t rc = console_dcc_register(); 86 if (rc == 0) { 87 panic(); 88 } 89 } else { 90 ERROR("BL31: No console device found.\n"); 91 } 92 /* Initialize the platform config for future decision making */ 93 zynqmp_config_setup(); 94 95 /* There are no parameters from BL2 if BL31 is a reset vector */ 96 assert(arg0 == 0U); 97 assert(arg1 == 0U); 98 99 /* 100 * Do initial security configuration to allow DRAM/device access. On 101 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but 102 * other platforms might have more programmable security devices 103 * present. 104 */ 105 106 /* Populate common information for BL32 and BL33 */ 107 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 108 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 109 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 110 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 111 112 atf_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); 113 114 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { 115 bl31_set_default_config(); 116 } else { 117 /* use parameters from FSBL */ 118 enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, 119 &bl33_image_ep_info, 120 atf_handoff_addr); 121 if (ret == FSBL_HANDOFF_NO_STRUCT) { 122 bl31_set_default_config(); 123 } else if (ret != FSBL_HANDOFF_SUCCESS) { 124 panic(); 125 } 126 } 127 if (bl32_image_ep_info.pc != 0) { 128 VERBOSE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 129 } 130 if (bl33_image_ep_info.pc != 0) { 131 VERBOSE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 132 } 133 } 134 135 #if ZYNQMP_WDT_RESTART 136 static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3]; 137 138 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 139 { 140 /* Validate 'handler' and 'id' parameters */ 141 if (!handler || id >= MAX_INTR_EL3) { 142 return -EINVAL; 143 } 144 145 /* Check if a handler has already been registered */ 146 if (type_el3_interrupt_table[id]) { 147 return -EALREADY; 148 } 149 150 type_el3_interrupt_table[id] = handler; 151 152 return 0; 153 } 154 155 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 156 void *handle, void *cookie) 157 { 158 uint32_t intr_id; 159 interrupt_type_handler_t handler; 160 161 intr_id = plat_ic_get_pending_interrupt_id(); 162 handler = type_el3_interrupt_table[intr_id]; 163 if (handler != NULL) { 164 handler(intr_id, flags, handle, cookie); 165 } 166 167 return 0; 168 } 169 #endif 170 171 #if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) 172 static void prepare_dtb(void) 173 { 174 void *dtb = (void *)XILINX_OF_BOARD_DTB_ADDR; 175 int ret; 176 177 /* Return if no device tree is detected */ 178 if (fdt_check_header(dtb) != 0) { 179 NOTICE("Can't read DT at %p\n", dtb); 180 return; 181 } 182 183 ret = fdt_open_into(dtb, dtb, XILINX_OF_BOARD_DTB_MAX_SIZE); 184 if (ret < 0) { 185 ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret); 186 return; 187 } 188 189 if (dt_add_psci_node(dtb)) { 190 ERROR("Failed to add PSCI Device Tree node\n"); 191 return; 192 } 193 194 if (dt_add_psci_cpu_enable_methods(dtb)) { 195 ERROR("Failed to add PSCI cpu enable methods in Device Tree\n"); 196 return; 197 } 198 199 /* Reserve memory used by Trusted Firmware. */ 200 if (fdt_add_reserved_memory(dtb, "tf-a", BL31_BASE, BL31_LIMIT - BL31_BASE)) { 201 WARN("Failed to add reserved memory nodes to DT.\n"); 202 } 203 204 ret = fdt_pack(dtb); 205 if (ret < 0) { 206 ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret); 207 } 208 209 clean_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb)); 210 INFO("Changed device tree to advertise PSCI and reserved memories.\n"); 211 } 212 #endif 213 214 void bl31_platform_setup(void) 215 { 216 #if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) 217 prepare_dtb(); 218 #endif 219 220 /* Initialize the gic cpu and distributor interfaces */ 221 plat_arm_gic_driver_init(); 222 plat_arm_gic_init(); 223 } 224 225 void bl31_plat_runtime_setup(void) 226 { 227 #if ZYNQMP_WDT_RESTART 228 uint64_t flags = 0; 229 uint64_t rc; 230 231 set_interrupt_rm_flag(flags, NON_SECURE); 232 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 233 rdo_el3_interrupt_handler, flags); 234 if (rc) { 235 panic(); 236 } 237 #endif 238 } 239 240 /* 241 * Perform the very early platform specific architectural setup here. 242 */ 243 void bl31_plat_arch_setup(void) 244 { 245 plat_arm_interconnect_init(); 246 plat_arm_interconnect_enter_coherency(); 247 248 249 const mmap_region_t bl_regions[] = { 250 #if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) 251 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 252 MT_MEMORY | MT_RW | MT_NS), 253 #endif 254 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 255 MT_MEMORY | MT_RW | MT_SECURE), 256 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 257 MT_CODE | MT_SECURE), 258 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 259 MT_RO_DATA | MT_SECURE), 260 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 261 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 262 MT_DEVICE | MT_RW | MT_SECURE), 263 {0} 264 }; 265 266 setup_page_tables(bl_regions, plat_arm_get_mmap()); 267 enable_mmu_el3(0); 268 } 269