1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <bl31/bl31.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/console.h> 14 #include <plat_arm.h> 15 #include <plat_private.h> 16 #include <plat/common/platform.h> 17 18 #define BL31_END (unsigned long)(&__BL31_END__) 19 20 static entry_point_info_t bl32_image_ep_info; 21 static entry_point_info_t bl33_image_ep_info; 22 23 /* 24 * Return a pointer to the 'entry_point_info' structure of the next image for 25 * the security state specified. BL33 corresponds to the non-secure image type 26 * while BL32 corresponds to the secure image type. A NULL pointer is returned 27 * if the image does not exist. 28 */ 29 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 30 { 31 assert(sec_state_is_valid(type)); 32 33 if (type == NON_SECURE) 34 return &bl33_image_ep_info; 35 36 return &bl32_image_ep_info; 37 } 38 39 /* 40 * Set the build time defaults. We want to do this when doing a JTAG boot 41 * or if we can't find any other config data. 42 */ 43 static inline void bl31_set_default_config(void) 44 { 45 bl32_image_ep_info.pc = BL32_BASE; 46 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 47 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 48 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 49 DISABLE_ALL_EXCEPTIONS); 50 } 51 52 /* 53 * Perform any BL31 specific platform actions. Here is an opportunity to copy 54 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 55 * are lost (potentially). This needs to be done before the MMU is initialized 56 * so that the memory layout can be used while creating page tables. 57 */ 58 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 59 u_register_t arg2, u_register_t arg3) 60 { 61 /* Initialize the console to provide early debug support */ 62 console_init(ZYNQMP_UART_BASE, zynqmp_get_uart_clk(), 63 ZYNQMP_UART_BAUDRATE); 64 65 /* Initialize the platform config for future decision making */ 66 zynqmp_config_setup(); 67 68 /* There are no parameters from BL2 if BL31 is a reset vector */ 69 assert(arg0 == 0U); 70 assert(arg1 == 0U); 71 72 /* 73 * Do initial security configuration to allow DRAM/device access. On 74 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but 75 * other platforms might have more programmable security devices 76 * present. 77 */ 78 79 /* Populate common information for BL32 and BL33 */ 80 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 81 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 82 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 83 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 84 85 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { 86 bl31_set_default_config(); 87 } else { 88 /* use parameters from FSBL */ 89 enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, 90 &bl33_image_ep_info); 91 if (ret == FSBL_HANDOFF_NO_STRUCT) 92 bl31_set_default_config(); 93 else if (ret != FSBL_HANDOFF_SUCCESS) 94 panic(); 95 } 96 97 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 98 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 99 } 100 101 /* Enable the test setup */ 102 #ifndef ZYNQMP_TESTING 103 static void zynqmp_testing_setup(void) { } 104 #else 105 static void zynqmp_testing_setup(void) 106 { 107 uint32_t actlr_el3, actlr_el2; 108 109 /* Enable CPU ACTLR AND L2ACTLR RW access from non-secure world */ 110 actlr_el3 = read_actlr_el3(); 111 actlr_el2 = read_actlr_el2(); 112 113 actlr_el3 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; 114 actlr_el2 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; 115 write_actlr_el3(actlr_el3); 116 write_actlr_el2(actlr_el2); 117 } 118 #endif 119 120 #if ZYNQMP_WDT_RESTART 121 static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3]; 122 123 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 124 { 125 /* Validate 'handler' and 'id' parameters */ 126 if (!handler || id >= MAX_INTR_EL3) 127 return -EINVAL; 128 129 /* Check if a handler has already been registered */ 130 if (type_el3_interrupt_table[id]) 131 return -EALREADY; 132 133 type_el3_interrupt_table[id] = handler; 134 135 return 0; 136 } 137 138 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 139 void *handle, void *cookie) 140 { 141 uint32_t intr_id; 142 interrupt_type_handler_t handler; 143 144 intr_id = plat_ic_get_pending_interrupt_id(); 145 handler = type_el3_interrupt_table[intr_id]; 146 if (handler != NULL) 147 handler(intr_id, flags, handle, cookie); 148 149 return 0; 150 } 151 #endif 152 153 void bl31_platform_setup(void) 154 { 155 /* Initialize the gic cpu and distributor interfaces */ 156 plat_arm_gic_driver_init(); 157 plat_arm_gic_init(); 158 zynqmp_testing_setup(); 159 } 160 161 void bl31_plat_runtime_setup(void) 162 { 163 #if ZYNQMP_WDT_RESTART 164 uint64_t flags = 0; 165 uint64_t rc; 166 167 set_interrupt_rm_flag(flags, NON_SECURE); 168 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 169 rdo_el3_interrupt_handler, flags); 170 if (rc) 171 panic(); 172 #endif 173 } 174 175 /* 176 * Perform the very early platform specific architectural setup here. 177 */ 178 void bl31_plat_arch_setup(void) 179 { 180 plat_arm_interconnect_init(); 181 plat_arm_interconnect_enter_coherency(); 182 183 184 const mmap_region_t bl_regions[] = { 185 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 186 MT_MEMORY | MT_RW | MT_SECURE), 187 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 188 MT_CODE | MT_SECURE), 189 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 190 MT_RO_DATA | MT_SECURE), 191 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 192 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 193 MT_DEVICE | MT_RW | MT_SECURE), 194 {0} 195 }; 196 197 setup_page_tables(bl_regions, plat_arm_get_mmap()); 198 enable_mmu_el3(0); 199 } 200