1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <bl31/bl31.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/console.h> 14 #include <plat/arm/common/plat_arm.h> 15 #include <plat/common/platform.h> 16 #include <lib/mmio.h> 17 18 #include <plat_startup.h> 19 #include <plat_private.h> 20 #include <zynqmp_def.h> 21 22 static entry_point_info_t bl32_image_ep_info; 23 static entry_point_info_t bl33_image_ep_info; 24 25 /* 26 * Return a pointer to the 'entry_point_info' structure of the next image for 27 * the security state specified. BL33 corresponds to the non-secure image type 28 * while BL32 corresponds to the secure image type. A NULL pointer is returned 29 * if the image does not exist. 30 */ 31 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 32 { 33 assert(sec_state_is_valid(type)); 34 35 if (type == NON_SECURE) { 36 return &bl33_image_ep_info; 37 } 38 39 return &bl32_image_ep_info; 40 } 41 42 /* 43 * Set the build time defaults. We want to do this when doing a JTAG boot 44 * or if we can't find any other config data. 45 */ 46 static inline void bl31_set_default_config(void) 47 { 48 bl32_image_ep_info.pc = BL32_BASE; 49 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 50 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 51 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 52 DISABLE_ALL_EXCEPTIONS); 53 } 54 55 /* 56 * Perform any BL31 specific platform actions. Here is an opportunity to copy 57 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 58 * are lost (potentially). This needs to be done before the MMU is initialized 59 * so that the memory layout can be used while creating page tables. 60 */ 61 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 62 u_register_t arg2, u_register_t arg3) 63 { 64 uint64_t atf_handoff_addr; 65 /* Register the console to provide early debug support */ 66 static console_t bl31_boot_console; 67 (void)console_cdns_register(ZYNQMP_UART_BASE, 68 zynqmp_get_uart_clk(), 69 ZYNQMP_UART_BAUDRATE, 70 &bl31_boot_console); 71 console_set_scope(&bl31_boot_console, 72 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT); 73 74 /* Initialize the platform config for future decision making */ 75 zynqmp_config_setup(); 76 77 /* There are no parameters from BL2 if BL31 is a reset vector */ 78 assert(arg0 == 0U); 79 assert(arg1 == 0U); 80 81 /* 82 * Do initial security configuration to allow DRAM/device access. On 83 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but 84 * other platforms might have more programmable security devices 85 * present. 86 */ 87 88 /* Populate common information for BL32 and BL33 */ 89 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 90 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 91 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 92 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 93 94 atf_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); 95 96 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { 97 bl31_set_default_config(); 98 } else { 99 /* use parameters from FSBL */ 100 enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, 101 &bl33_image_ep_info, 102 atf_handoff_addr); 103 if (ret == FSBL_HANDOFF_NO_STRUCT) { 104 bl31_set_default_config(); 105 } else if (ret != FSBL_HANDOFF_SUCCESS) { 106 panic(); 107 } 108 } 109 if (bl32_image_ep_info.pc) { 110 VERBOSE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 111 } 112 if (bl33_image_ep_info.pc) { 113 VERBOSE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 114 } 115 } 116 117 /* Enable the test setup */ 118 #ifndef ZYNQMP_TESTING 119 static void zynqmp_testing_setup(void) { } 120 #else 121 static void zynqmp_testing_setup(void) 122 { 123 uint32_t actlr_el3, actlr_el2; 124 125 /* Enable CPU ACTLR AND L2ACTLR RW access from non-secure world */ 126 actlr_el3 = read_actlr_el3(); 127 actlr_el2 = read_actlr_el2(); 128 129 actlr_el3 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; 130 actlr_el2 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; 131 write_actlr_el3(actlr_el3); 132 write_actlr_el2(actlr_el2); 133 } 134 #endif 135 136 #if ZYNQMP_WDT_RESTART 137 static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3]; 138 139 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 140 { 141 /* Validate 'handler' and 'id' parameters */ 142 if (!handler || id >= MAX_INTR_EL3) { 143 return -EINVAL; 144 } 145 146 /* Check if a handler has already been registered */ 147 if (type_el3_interrupt_table[id]) { 148 return -EALREADY; 149 } 150 151 type_el3_interrupt_table[id] = handler; 152 153 return 0; 154 } 155 156 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 157 void *handle, void *cookie) 158 { 159 uint32_t intr_id; 160 interrupt_type_handler_t handler; 161 162 intr_id = plat_ic_get_pending_interrupt_id(); 163 handler = type_el3_interrupt_table[intr_id]; 164 if (handler != NULL) { 165 handler(intr_id, flags, handle, cookie); 166 } 167 168 return 0; 169 } 170 #endif 171 172 void bl31_platform_setup(void) 173 { 174 /* Initialize the gic cpu and distributor interfaces */ 175 plat_arm_gic_driver_init(); 176 plat_arm_gic_init(); 177 zynqmp_testing_setup(); 178 } 179 180 void bl31_plat_runtime_setup(void) 181 { 182 #if ZYNQMP_WDT_RESTART 183 uint64_t flags = 0; 184 uint64_t rc; 185 186 set_interrupt_rm_flag(flags, NON_SECURE); 187 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 188 rdo_el3_interrupt_handler, flags); 189 if (rc) { 190 panic(); 191 } 192 #endif 193 } 194 195 /* 196 * Perform the very early platform specific architectural setup here. 197 */ 198 void bl31_plat_arch_setup(void) 199 { 200 plat_arm_interconnect_init(); 201 plat_arm_interconnect_enter_coherency(); 202 203 204 const mmap_region_t bl_regions[] = { 205 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 206 MT_MEMORY | MT_RW | MT_SECURE), 207 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 208 MT_CODE | MT_SECURE), 209 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 210 MT_RO_DATA | MT_SECURE), 211 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 212 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 213 MT_DEVICE | MT_RW | MT_SECURE), 214 {0} 215 }; 216 217 setup_page_tables(bl_regions, plat_arm_get_mmap()); 218 enable_mmu_el3(0); 219 } 220