1 /* 2 * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 11 #include <bl31/bl31.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/fdt_fixup.h> 15 #include <common/fdt_wrappers.h> 16 #include <lib/mmio.h> 17 #include <libfdt.h> 18 #include <plat/arm/common/plat_arm.h> 19 #include <plat/common/platform.h> 20 #include <plat_console.h> 21 22 #include <custom_svc.h> 23 #include <plat_fdt.h> 24 #include <plat_private.h> 25 #include <plat_startup.h> 26 #include <zynqmp_def.h> 27 28 29 static entry_point_info_t bl32_image_ep_info; 30 static entry_point_info_t bl33_image_ep_info; 31 32 /* 33 * Return a pointer to the 'entry_point_info' structure of the next image for 34 * the security state specified. BL33 corresponds to the non-secure image type 35 * while BL32 corresponds to the secure image type. A NULL pointer is returned 36 * if the image does not exist. 37 */ 38 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 39 { 40 entry_point_info_t *next_image_info; 41 42 assert(sec_state_is_valid(type)); 43 if (type == NON_SECURE) { 44 next_image_info = &bl33_image_ep_info; 45 } else { 46 next_image_info = &bl32_image_ep_info; 47 } 48 49 return next_image_info; 50 } 51 52 /* 53 * Set the build time defaults. We want to do this when doing a JTAG boot 54 * or if we can't find any other config data. 55 */ 56 static inline void bl31_set_default_config(void) 57 { 58 bl32_image_ep_info.pc = BL32_BASE; 59 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 60 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 61 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 62 DISABLE_ALL_EXCEPTIONS); 63 } 64 65 /* 66 * Perform any BL31 specific platform actions. Here is an opportunity to copy 67 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 68 * are lost (potentially). This needs to be done before the MMU is initialized 69 * so that the memory layout can be used while creating page tables. 70 */ 71 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 72 u_register_t arg2, u_register_t arg3) 73 { 74 uint64_t tfa_handoff_addr; 75 76 setup_console(); 77 78 /* Initialize the platform config for future decision making */ 79 zynqmp_config_setup(); 80 81 /* 82 * Do initial security configuration to allow DRAM/device access. On 83 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but 84 * other platforms might have more programmable security devices 85 * present. 86 */ 87 88 /* Populate common information for BL32 and BL33 */ 89 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 90 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 91 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 92 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 93 94 tfa_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); 95 96 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { 97 bl31_set_default_config(); 98 } else { 99 /* use parameters from XBL */ 100 enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info, 101 &bl33_image_ep_info, 102 tfa_handoff_addr); 103 if (ret != XBL_HANDOFF_SUCCESS) { 104 panic(); 105 } 106 } 107 if (bl32_image_ep_info.pc != 0) { 108 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 109 } 110 if (bl33_image_ep_info.pc != 0) { 111 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 112 } 113 114 custom_early_setup(); 115 116 } 117 118 #if ZYNQMP_WDT_RESTART 119 static zynmp_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 120 121 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 122 { 123 static uint32_t index; 124 uint32_t i; 125 126 /* Validate 'handler' and 'id' parameters */ 127 if (!handler || index >= MAX_INTR_EL3) { 128 return -EINVAL; 129 } 130 131 /* Check if a handler has already been registered */ 132 for (i = 0; i < index; i++) { 133 if (id == type_el3_interrupt_table[i].id) { 134 return -EALREADY; 135 } 136 } 137 138 type_el3_interrupt_table[index].id = id; 139 type_el3_interrupt_table[index].handler = handler; 140 141 index++; 142 143 return 0; 144 } 145 146 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 147 void *handle, void *cookie) 148 { 149 uint32_t intr_id; 150 uint32_t i; 151 interrupt_type_handler_t handler = NULL; 152 153 intr_id = plat_ic_get_pending_interrupt_id(); 154 155 for (i = 0; i < MAX_INTR_EL3; i++) { 156 if (intr_id == type_el3_interrupt_table[i].id) { 157 handler = type_el3_interrupt_table[i].handler; 158 } 159 } 160 161 if (handler != NULL) { 162 return handler(intr_id, flags, handle, cookie); 163 } 164 165 return 0; 166 } 167 #endif 168 169 void bl31_platform_setup(void) 170 { 171 prepare_dtb(); 172 173 /* Initialize the gic cpu and distributor interfaces */ 174 plat_arm_gic_driver_init(); 175 plat_arm_gic_init(); 176 } 177 178 void bl31_plat_runtime_setup(void) 179 { 180 #if ZYNQMP_WDT_RESTART 181 uint64_t flags = 0; 182 uint64_t rc; 183 184 set_interrupt_rm_flag(flags, NON_SECURE); 185 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 186 rdo_el3_interrupt_handler, flags); 187 if (rc) { 188 panic(); 189 } 190 #endif 191 192 custom_runtime_setup(); 193 194 console_switch_state(CONSOLE_FLAG_RUNTIME); 195 } 196 197 /* 198 * Perform the very early platform specific architectural setup here. 199 */ 200 void bl31_plat_arch_setup(void) 201 { 202 plat_arm_interconnect_init(); 203 plat_arm_interconnect_enter_coherency(); 204 205 const mmap_region_t bl_regions[] = { 206 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 207 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 208 MT_MEMORY | MT_RW | MT_NS), 209 #endif 210 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 211 MT_MEMORY | MT_RW | MT_SECURE), 212 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 213 MT_CODE | MT_SECURE), 214 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 215 MT_RO_DATA | MT_SECURE), 216 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 217 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 218 MT_DEVICE | MT_RW | MT_SECURE), 219 {0} 220 }; 221 222 custom_mmap_add(); 223 224 setup_page_tables(bl_regions, plat_get_mmap()); 225 enable_mmu_el3(0); 226 } 227