1 /* 2 * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 11 #include <bl31/bl31.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <drivers/arm/dcc.h> 15 #include <drivers/console.h> 16 #include <plat/arm/common/plat_arm.h> 17 #include <plat/common/platform.h> 18 #include <lib/mmio.h> 19 20 #include <custom_svc.h> 21 #include <plat_startup.h> 22 #include <plat_private.h> 23 #include <zynqmp_def.h> 24 25 #include <common/fdt_fixup.h> 26 #include <common/fdt_wrappers.h> 27 #include <libfdt.h> 28 29 static entry_point_info_t bl32_image_ep_info; 30 static entry_point_info_t bl33_image_ep_info; 31 32 /* 33 * Return a pointer to the 'entry_point_info' structure of the next image for 34 * the security state specified. BL33 corresponds to the non-secure image type 35 * while BL32 corresponds to the secure image type. A NULL pointer is returned 36 * if the image does not exist. 37 */ 38 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 39 { 40 entry_point_info_t *next_image_info; 41 42 assert(sec_state_is_valid(type)); 43 if (type == NON_SECURE) { 44 next_image_info = &bl33_image_ep_info; 45 } else { 46 next_image_info = &bl32_image_ep_info; 47 } 48 49 return next_image_info; 50 } 51 52 /* 53 * Set the build time defaults. We want to do this when doing a JTAG boot 54 * or if we can't find any other config data. 55 */ 56 static inline void bl31_set_default_config(void) 57 { 58 bl32_image_ep_info.pc = BL32_BASE; 59 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 60 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 61 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 62 DISABLE_ALL_EXCEPTIONS); 63 } 64 65 /* 66 * Perform any BL31 specific platform actions. Here is an opportunity to copy 67 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 68 * are lost (potentially). This needs to be done before the MMU is initialized 69 * so that the memory layout can be used while creating page tables. 70 */ 71 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 72 u_register_t arg2, u_register_t arg3) 73 { 74 uint64_t tfa_handoff_addr; 75 76 if (ZYNQMP_CONSOLE_IS(cadence) || (ZYNQMP_CONSOLE_IS(cadence1))) { 77 /* Register the console to provide early debug support */ 78 static console_t bl31_boot_console; 79 (void)console_cdns_register(ZYNQMP_UART_BASE, 80 zynqmp_get_uart_clk(), 81 ZYNQMP_UART_BAUDRATE, 82 &bl31_boot_console); 83 console_set_scope(&bl31_boot_console, 84 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT); 85 } else if (ZYNQMP_CONSOLE_IS(dcc)) { 86 /* Initialize the dcc console for debug */ 87 int32_t rc = console_dcc_register(); 88 if (rc == 0) { 89 panic(); 90 } 91 } else { 92 ERROR("BL31: No console device found.\n"); 93 } 94 /* Initialize the platform config for future decision making */ 95 zynqmp_config_setup(); 96 97 /* 98 * Do initial security configuration to allow DRAM/device access. On 99 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but 100 * other platforms might have more programmable security devices 101 * present. 102 */ 103 104 /* Populate common information for BL32 and BL33 */ 105 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 106 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 107 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 108 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 109 110 tfa_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); 111 112 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { 113 bl31_set_default_config(); 114 } else { 115 /* use parameters from FSBL */ 116 enum fsbl_handoff ret = fsbl_tfa_handover(&bl32_image_ep_info, 117 &bl33_image_ep_info, 118 tfa_handoff_addr); 119 if (ret != FSBL_HANDOFF_SUCCESS) { 120 panic(); 121 } 122 } 123 if (bl32_image_ep_info.pc != 0) { 124 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 125 } 126 if (bl33_image_ep_info.pc != 0) { 127 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 128 } 129 130 custom_early_setup(); 131 132 } 133 134 #if ZYNQMP_WDT_RESTART 135 static zynmp_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 136 137 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 138 { 139 static uint32_t index; 140 uint32_t i; 141 142 /* Validate 'handler' and 'id' parameters */ 143 if (!handler || index >= MAX_INTR_EL3) { 144 return -EINVAL; 145 } 146 147 /* Check if a handler has already been registered */ 148 for (i = 0; i < index; i++) { 149 if (id == type_el3_interrupt_table[i].id) { 150 return -EALREADY; 151 } 152 } 153 154 type_el3_interrupt_table[index].id = id; 155 type_el3_interrupt_table[index].handler = handler; 156 157 index++; 158 159 return 0; 160 } 161 162 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 163 void *handle, void *cookie) 164 { 165 uint32_t intr_id; 166 uint32_t i; 167 interrupt_type_handler_t handler = NULL; 168 169 intr_id = plat_ic_get_pending_interrupt_id(); 170 171 for (i = 0; i < MAX_INTR_EL3; i++) { 172 if (intr_id == type_el3_interrupt_table[i].id) { 173 handler = type_el3_interrupt_table[i].handler; 174 } 175 } 176 177 if (handler != NULL) { 178 return handler(intr_id, flags, handle, cookie); 179 } 180 181 return 0; 182 } 183 #endif 184 185 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 186 static void prepare_dtb(void) 187 { 188 void *dtb = (void *)XILINX_OF_BOARD_DTB_ADDR; 189 int ret; 190 191 /* Return if no device tree is detected */ 192 if (fdt_check_header(dtb) != 0) { 193 NOTICE("Can't read DT at %p\n", dtb); 194 return; 195 } 196 197 ret = fdt_open_into(dtb, dtb, XILINX_OF_BOARD_DTB_MAX_SIZE); 198 if (ret < 0) { 199 ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret); 200 return; 201 } 202 203 if (dt_add_psci_node(dtb)) { 204 ERROR("Failed to add PSCI Device Tree node\n"); 205 return; 206 } 207 208 if (dt_add_psci_cpu_enable_methods(dtb)) { 209 ERROR("Failed to add PSCI cpu enable methods in Device Tree\n"); 210 return; 211 } 212 213 /* Reserve memory used by Trusted Firmware. */ 214 if (fdt_add_reserved_memory(dtb, "tf-a", BL31_BASE, 215 (size_t) (BL31_LIMIT - BL31_BASE))) { 216 WARN("Failed to add reserved memory nodes for BL31 to DT.\n"); 217 } 218 219 ret = fdt_pack(dtb); 220 if (ret < 0) { 221 ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret); 222 } 223 224 clean_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb)); 225 INFO("Changed device tree to advertise PSCI and reserved memories.\n"); 226 } 227 #endif 228 229 void bl31_platform_setup(void) 230 { 231 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 232 prepare_dtb(); 233 #endif 234 235 /* Initialize the gic cpu and distributor interfaces */ 236 plat_arm_gic_driver_init(); 237 plat_arm_gic_init(); 238 } 239 240 void bl31_plat_runtime_setup(void) 241 { 242 #if ZYNQMP_WDT_RESTART 243 uint64_t flags = 0; 244 uint64_t rc; 245 246 set_interrupt_rm_flag(flags, NON_SECURE); 247 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 248 rdo_el3_interrupt_handler, flags); 249 if (rc) { 250 panic(); 251 } 252 #endif 253 254 custom_runtime_setup(); 255 } 256 257 /* 258 * Perform the very early platform specific architectural setup here. 259 */ 260 void bl31_plat_arch_setup(void) 261 { 262 plat_arm_interconnect_init(); 263 plat_arm_interconnect_enter_coherency(); 264 265 const mmap_region_t bl_regions[] = { 266 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 267 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 268 MT_MEMORY | MT_RW | MT_NS), 269 #endif 270 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 271 MT_MEMORY | MT_RW | MT_SECURE), 272 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 273 MT_CODE | MT_SECURE), 274 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 275 MT_RO_DATA | MT_SECURE), 276 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 277 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 278 MT_DEVICE | MT_RW | MT_SECURE), 279 {0} 280 }; 281 282 custom_mmap_add(); 283 284 setup_page_tables(bl_regions, plat_arm_get_mmap()); 285 enable_mmu_el3(0); 286 } 287