1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <bl31/bl31.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/console.h> 14 #include <plat/arm/common/plat_arm.h> 15 #include <plat/common/platform.h> 16 #include <lib/mmio.h> 17 18 #include <plat_startup.h> 19 #include <plat_private.h> 20 #include <zynqmp_def.h> 21 22 static entry_point_info_t bl32_image_ep_info; 23 static entry_point_info_t bl33_image_ep_info; 24 25 /* 26 * Return a pointer to the 'entry_point_info' structure of the next image for 27 * the security state specified. BL33 corresponds to the non-secure image type 28 * while BL32 corresponds to the secure image type. A NULL pointer is returned 29 * if the image does not exist. 30 */ 31 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 32 { 33 assert(sec_state_is_valid(type)); 34 35 if (type == NON_SECURE) 36 return &bl33_image_ep_info; 37 38 return &bl32_image_ep_info; 39 } 40 41 /* 42 * Set the build time defaults. We want to do this when doing a JTAG boot 43 * or if we can't find any other config data. 44 */ 45 static inline void bl31_set_default_config(void) 46 { 47 bl32_image_ep_info.pc = BL32_BASE; 48 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 49 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 50 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 51 DISABLE_ALL_EXCEPTIONS); 52 } 53 54 /* 55 * Perform any BL31 specific platform actions. Here is an opportunity to copy 56 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 57 * are lost (potentially). This needs to be done before the MMU is initialized 58 * so that the memory layout can be used while creating page tables. 59 */ 60 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 61 u_register_t arg2, u_register_t arg3) 62 { 63 uint64_t atf_handoff_addr; 64 /* Register the console to provide early debug support */ 65 static console_t bl31_boot_console; 66 (void)console_cdns_register(ZYNQMP_UART_BASE, 67 zynqmp_get_uart_clk(), 68 ZYNQMP_UART_BAUDRATE, 69 &bl31_boot_console); 70 console_set_scope(&bl31_boot_console, 71 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT); 72 73 /* Initialize the platform config for future decision making */ 74 zynqmp_config_setup(); 75 76 /* There are no parameters from BL2 if BL31 is a reset vector */ 77 assert(arg0 == 0U); 78 assert(arg1 == 0U); 79 80 /* 81 * Do initial security configuration to allow DRAM/device access. On 82 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but 83 * other platforms might have more programmable security devices 84 * present. 85 */ 86 87 /* Populate common information for BL32 and BL33 */ 88 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 89 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 90 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 91 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 92 93 atf_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); 94 95 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { 96 bl31_set_default_config(); 97 } else { 98 /* use parameters from FSBL */ 99 enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, 100 &bl33_image_ep_info, 101 atf_handoff_addr); 102 if (ret == FSBL_HANDOFF_NO_STRUCT) 103 bl31_set_default_config(); 104 else if (ret != FSBL_HANDOFF_SUCCESS) 105 panic(); 106 } 107 if (bl32_image_ep_info.pc) { 108 VERBOSE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 109 } 110 if (bl33_image_ep_info.pc) { 111 VERBOSE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 112 } 113 } 114 115 /* Enable the test setup */ 116 #ifndef ZYNQMP_TESTING 117 static void zynqmp_testing_setup(void) { } 118 #else 119 static void zynqmp_testing_setup(void) 120 { 121 uint32_t actlr_el3, actlr_el2; 122 123 /* Enable CPU ACTLR AND L2ACTLR RW access from non-secure world */ 124 actlr_el3 = read_actlr_el3(); 125 actlr_el2 = read_actlr_el2(); 126 127 actlr_el3 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; 128 actlr_el2 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; 129 write_actlr_el3(actlr_el3); 130 write_actlr_el2(actlr_el2); 131 } 132 #endif 133 134 #if ZYNQMP_WDT_RESTART 135 static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3]; 136 137 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 138 { 139 /* Validate 'handler' and 'id' parameters */ 140 if (!handler || id >= MAX_INTR_EL3) 141 return -EINVAL; 142 143 /* Check if a handler has already been registered */ 144 if (type_el3_interrupt_table[id]) 145 return -EALREADY; 146 147 type_el3_interrupt_table[id] = handler; 148 149 return 0; 150 } 151 152 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 153 void *handle, void *cookie) 154 { 155 uint32_t intr_id; 156 interrupt_type_handler_t handler; 157 158 intr_id = plat_ic_get_pending_interrupt_id(); 159 handler = type_el3_interrupt_table[intr_id]; 160 if (handler != NULL) 161 handler(intr_id, flags, handle, cookie); 162 163 return 0; 164 } 165 #endif 166 167 void bl31_platform_setup(void) 168 { 169 /* Initialize the gic cpu and distributor interfaces */ 170 plat_arm_gic_driver_init(); 171 plat_arm_gic_init(); 172 zynqmp_testing_setup(); 173 } 174 175 void bl31_plat_runtime_setup(void) 176 { 177 #if ZYNQMP_WDT_RESTART 178 uint64_t flags = 0; 179 uint64_t rc; 180 181 set_interrupt_rm_flag(flags, NON_SECURE); 182 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 183 rdo_el3_interrupt_handler, flags); 184 if (rc) 185 panic(); 186 #endif 187 } 188 189 /* 190 * Perform the very early platform specific architectural setup here. 191 */ 192 void bl31_plat_arch_setup(void) 193 { 194 plat_arm_interconnect_init(); 195 plat_arm_interconnect_enter_coherency(); 196 197 198 const mmap_region_t bl_regions[] = { 199 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 200 MT_MEMORY | MT_RW | MT_SECURE), 201 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 202 MT_CODE | MT_SECURE), 203 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 204 MT_RO_DATA | MT_SECURE), 205 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 206 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 207 MT_DEVICE | MT_RW | MT_SECURE), 208 {0} 209 }; 210 211 setup_page_tables(bl_regions, plat_arm_get_mmap()); 212 enable_mmu_el3(0); 213 } 214