1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <assert.h> 32 #include <bl_common.h> 33 #include <bl31.h> 34 #include <console.h> 35 #include <debug.h> 36 #include <errno.h> 37 #include <plat_arm.h> 38 #include <platform.h> 39 #include "zynqmp_private.h" 40 41 #define BL31_END (unsigned long)(&__BL31_END__) 42 43 static entry_point_info_t bl32_image_ep_info; 44 static entry_point_info_t bl33_image_ep_info; 45 46 /* 47 * Return a pointer to the 'entry_point_info' structure of the next image for 48 * the security state specified. BL33 corresponds to the non-secure image type 49 * while BL32 corresponds to the secure image type. A NULL pointer is returned 50 * if the image does not exist. 51 */ 52 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 53 { 54 assert(sec_state_is_valid(type)); 55 56 if (type == NON_SECURE) 57 return &bl33_image_ep_info; 58 59 return &bl32_image_ep_info; 60 } 61 62 /* 63 * Perform any BL31 specific platform actions. Here is an opportunity to copy 64 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 65 * are lost (potentially). This needs to be done before the MMU is initialized 66 * so that the memory layout can be used while creating page tables. 67 */ 68 void bl31_early_platform_setup(bl31_params_t *from_bl2, 69 void *plat_params_from_bl2) 70 { 71 /* Initialize the console to provide early debug support */ 72 console_init(ZYNQMP_UART_BASE, zynqmp_get_uart_clk(), 73 ZYNQMP_UART_BAUDRATE); 74 75 /* Initialize the platform config for future decision making */ 76 zynqmp_config_setup(); 77 78 /* There are no parameters from BL2 if BL31 is a reset vector */ 79 assert(from_bl2 == NULL); 80 assert(plat_params_from_bl2 == NULL); 81 82 /* 83 * Do initial security configuration to allow DRAM/device access. On 84 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but 85 * other platforms might have more programmable security devices 86 * present. 87 */ 88 89 /* Populate common information for BL32 and BL33 */ 90 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 91 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 92 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 93 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 94 95 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { 96 /* use build time defaults in JTAG boot mode */ 97 bl32_image_ep_info.pc = BL32_BASE; 98 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 99 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 100 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 101 DISABLE_ALL_EXCEPTIONS); 102 } else { 103 /* use parameters from FSBL */ 104 fsbl_atf_handover(&bl32_image_ep_info, &bl33_image_ep_info); 105 } 106 107 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 108 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 109 } 110 111 /* Enable the test setup */ 112 #ifndef ZYNQMP_TESTING 113 static void zynqmp_testing_setup(void) { } 114 #else 115 static void zynqmp_testing_setup(void) 116 { 117 uint32_t actlr_el3, actlr_el2; 118 119 /* Enable CPU ACTLR AND L2ACTLR RW access from non-secure world */ 120 actlr_el3 = read_actlr_el3(); 121 actlr_el2 = read_actlr_el2(); 122 123 actlr_el3 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; 124 actlr_el2 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; 125 write_actlr_el3(actlr_el3); 126 write_actlr_el2(actlr_el2); 127 } 128 #endif 129 130 void bl31_platform_setup(void) 131 { 132 /* Initialize the gic cpu and distributor interfaces */ 133 plat_arm_gic_driver_init(); 134 plat_arm_gic_init(); 135 zynqmp_testing_setup(); 136 } 137 138 void bl31_plat_runtime_setup(void) 139 { 140 } 141 142 /* 143 * Perform the very early platform specific architectural setup here. 144 */ 145 void bl31_plat_arch_setup(void) 146 { 147 plat_arm_interconnect_init(); 148 plat_arm_interconnect_enter_coherency(); 149 150 arm_setup_page_tables(BL31_BASE, 151 BL31_END - BL31_BASE, 152 BL_CODE_BASE, 153 BL_CODE_END, 154 BL_RO_DATA_BASE, 155 BL_RO_DATA_END, 156 BL_COHERENT_RAM_BASE, 157 BL_COHERENT_RAM_END); 158 enable_mmu_el3(0); 159 } 160