1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <bl31/bl31.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/console.h> 14 #include <plat/arm/common/plat_arm.h> 15 #include <plat/common/platform.h> 16 17 #include <plat_private.h> 18 19 static entry_point_info_t bl32_image_ep_info; 20 static entry_point_info_t bl33_image_ep_info; 21 22 /* 23 * Return a pointer to the 'entry_point_info' structure of the next image for 24 * the security state specified. BL33 corresponds to the non-secure image type 25 * while BL32 corresponds to the secure image type. A NULL pointer is returned 26 * if the image does not exist. 27 */ 28 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 29 { 30 assert(sec_state_is_valid(type)); 31 32 if (type == NON_SECURE) 33 return &bl33_image_ep_info; 34 35 return &bl32_image_ep_info; 36 } 37 38 /* 39 * Set the build time defaults. We want to do this when doing a JTAG boot 40 * or if we can't find any other config data. 41 */ 42 static inline void bl31_set_default_config(void) 43 { 44 bl32_image_ep_info.pc = BL32_BASE; 45 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 46 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 47 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 48 DISABLE_ALL_EXCEPTIONS); 49 } 50 51 /* 52 * Perform any BL31 specific platform actions. Here is an opportunity to copy 53 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 54 * are lost (potentially). This needs to be done before the MMU is initialized 55 * so that the memory layout can be used while creating page tables. 56 */ 57 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 58 u_register_t arg2, u_register_t arg3) 59 { 60 /* Register the console to provide early debug support */ 61 static console_cdns_t bl31_boot_console; 62 (void)console_cdns_register(ZYNQMP_UART_BASE, 63 zynqmp_get_uart_clk(), 64 ZYNQMP_UART_BAUDRATE, 65 &bl31_boot_console); 66 console_set_scope(&bl31_boot_console.console, 67 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT); 68 69 /* Initialize the platform config for future decision making */ 70 zynqmp_config_setup(); 71 72 /* There are no parameters from BL2 if BL31 is a reset vector */ 73 assert(arg0 == 0U); 74 assert(arg1 == 0U); 75 76 /* 77 * Do initial security configuration to allow DRAM/device access. On 78 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but 79 * other platforms might have more programmable security devices 80 * present. 81 */ 82 83 /* Populate common information for BL32 and BL33 */ 84 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 85 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 86 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 87 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 88 89 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { 90 bl31_set_default_config(); 91 } else { 92 /* use parameters from FSBL */ 93 enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, 94 &bl33_image_ep_info); 95 if (ret == FSBL_HANDOFF_NO_STRUCT) 96 bl31_set_default_config(); 97 else if (ret != FSBL_HANDOFF_SUCCESS) 98 panic(); 99 } 100 101 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 102 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 103 } 104 105 /* Enable the test setup */ 106 #ifndef ZYNQMP_TESTING 107 static void zynqmp_testing_setup(void) { } 108 #else 109 static void zynqmp_testing_setup(void) 110 { 111 uint32_t actlr_el3, actlr_el2; 112 113 /* Enable CPU ACTLR AND L2ACTLR RW access from non-secure world */ 114 actlr_el3 = read_actlr_el3(); 115 actlr_el2 = read_actlr_el2(); 116 117 actlr_el3 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; 118 actlr_el2 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; 119 write_actlr_el3(actlr_el3); 120 write_actlr_el2(actlr_el2); 121 } 122 #endif 123 124 #if ZYNQMP_WDT_RESTART 125 static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3]; 126 127 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 128 { 129 /* Validate 'handler' and 'id' parameters */ 130 if (!handler || id >= MAX_INTR_EL3) 131 return -EINVAL; 132 133 /* Check if a handler has already been registered */ 134 if (type_el3_interrupt_table[id]) 135 return -EALREADY; 136 137 type_el3_interrupt_table[id] = handler; 138 139 return 0; 140 } 141 142 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 143 void *handle, void *cookie) 144 { 145 uint32_t intr_id; 146 interrupt_type_handler_t handler; 147 148 intr_id = plat_ic_get_pending_interrupt_id(); 149 handler = type_el3_interrupt_table[intr_id]; 150 if (handler != NULL) 151 handler(intr_id, flags, handle, cookie); 152 153 return 0; 154 } 155 #endif 156 157 void bl31_platform_setup(void) 158 { 159 /* Initialize the gic cpu and distributor interfaces */ 160 plat_arm_gic_driver_init(); 161 plat_arm_gic_init(); 162 zynqmp_testing_setup(); 163 } 164 165 void bl31_plat_runtime_setup(void) 166 { 167 #if ZYNQMP_WDT_RESTART 168 uint64_t flags = 0; 169 uint64_t rc; 170 171 set_interrupt_rm_flag(flags, NON_SECURE); 172 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 173 rdo_el3_interrupt_handler, flags); 174 if (rc) 175 panic(); 176 #endif 177 } 178 179 /* 180 * Perform the very early platform specific architectural setup here. 181 */ 182 void bl31_plat_arch_setup(void) 183 { 184 plat_arm_interconnect_init(); 185 plat_arm_interconnect_enter_coherency(); 186 187 188 const mmap_region_t bl_regions[] = { 189 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 190 MT_MEMORY | MT_RW | MT_SECURE), 191 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 192 MT_CODE | MT_SECURE), 193 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 194 MT_RO_DATA | MT_SECURE), 195 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 196 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 197 MT_DEVICE | MT_RW | MT_SECURE), 198 {0} 199 }; 200 201 setup_page_tables(bl_regions, plat_arm_get_mmap()); 202 enable_mmu_el3(0); 203 } 204