1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 11 #include <bl31/bl31.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/fdt_fixup.h> 15 #include <common/fdt_wrappers.h> 16 #include <drivers/generic_delay_timer.h> 17 #include <lib/mmio.h> 18 #include <lib/xlat_tables/xlat_tables_v2.h> 19 #include <libfdt.h> 20 #include <plat/arm/common/plat_arm.h> 21 #include <plat/common/platform.h> 22 #include <plat_console.h> 23 24 #include <custom_svc.h> 25 #include <plat_fdt.h> 26 #include <plat_private.h> 27 #include <plat_startup.h> 28 #include <zynqmp_def.h> 29 30 31 static entry_point_info_t bl32_image_ep_info; 32 static entry_point_info_t bl33_image_ep_info; 33 34 /* 35 * Return a pointer to the 'entry_point_info' structure of the next image for 36 * the security state specified. BL33 corresponds to the non-secure image type 37 * while BL32 corresponds to the secure image type. A NULL pointer is returned 38 * if the image does not exist. 39 */ 40 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 41 { 42 entry_point_info_t *next_image_info; 43 44 assert(sec_state_is_valid(type)); 45 if (type == NON_SECURE) { 46 next_image_info = &bl33_image_ep_info; 47 } else { 48 next_image_info = &bl32_image_ep_info; 49 } 50 51 return next_image_info; 52 } 53 54 /* 55 * Set the build time defaults. We want to do this when doing a JTAG boot 56 * or if we can't find any other config data. 57 */ 58 static inline void bl31_set_default_config(void) 59 { 60 bl32_image_ep_info.pc = BL32_BASE; 61 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 62 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 63 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 64 DISABLE_ALL_EXCEPTIONS); 65 } 66 67 /* 68 * Perform any BL31 specific platform actions. Here is an opportunity to copy 69 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 70 * are lost (potentially). This needs to be done before the MMU is initialized 71 * so that the memory layout can be used while creating page tables. 72 */ 73 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 74 u_register_t arg2, u_register_t arg3) 75 { 76 (void)arg0; 77 (void)arg1; 78 (void)arg2; 79 (void)arg3; 80 uint64_t tfa_handoff_addr; 81 uint64_t counter_freq; 82 83 /* Configure counter frequency */ 84 counter_freq = read_cntfrq_el0(); 85 if (counter_freq == ZYNQMP_DEFAULT_COUNTER_FREQ) { 86 write_cntfrq_el0(plat_get_syscnt_freq2()); 87 } 88 89 generic_delay_timer_init(); 90 91 setup_console(); 92 93 /* Initialize the platform config for future decision making */ 94 zynqmp_config_setup(); 95 96 /* 97 * Do initial security configuration to allow DRAM/device access. On 98 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but 99 * other platforms might have more programmable security devices 100 * present. 101 */ 102 103 /* Populate common information for BL32 and BL33 */ 104 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 105 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 106 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 107 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 108 109 tfa_handoff_addr = (uint64_t)mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); 110 111 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { 112 bl31_set_default_config(); 113 } else { 114 /* use parameters from XBL */ 115 enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info, 116 &bl33_image_ep_info, 117 tfa_handoff_addr); 118 if (ret != XBL_HANDOFF_SUCCESS) { 119 panic(); 120 } 121 } 122 if (bl32_image_ep_info.pc != 0U) { 123 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 124 } 125 if (bl33_image_ep_info.pc != 0U) { 126 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 127 } 128 129 custom_early_setup(); 130 131 } 132 133 #if ZYNQMP_WDT_RESTART 134 static zynmp_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 135 136 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 137 { 138 static uint32_t index; 139 uint32_t i; 140 141 /* Validate 'handler' and 'id' parameters */ 142 if (!handler || index >= MAX_INTR_EL3) { 143 return -EINVAL; 144 } 145 146 /* Check if a handler has already been registered */ 147 for (i = 0; i < index; i++) { 148 if (id == type_el3_interrupt_table[i].id) { 149 return -EALREADY; 150 } 151 } 152 153 type_el3_interrupt_table[index].id = id; 154 type_el3_interrupt_table[index].handler = handler; 155 156 index++; 157 158 return 0; 159 } 160 161 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 162 void *handle, void *cookie) 163 { 164 uint32_t intr_id; 165 uint32_t i; 166 interrupt_type_handler_t handler = NULL; 167 168 intr_id = plat_ic_get_pending_interrupt_id(); 169 170 for (i = 0; i < MAX_INTR_EL3; i++) { 171 if (intr_id == type_el3_interrupt_table[i].id) { 172 handler = type_el3_interrupt_table[i].handler; 173 } 174 } 175 176 if (handler != NULL) { 177 return handler(intr_id, flags, handle, cookie); 178 } 179 180 return 0; 181 } 182 #endif 183 184 void bl31_platform_setup(void) 185 { 186 prepare_dtb(); 187 188 /* Initialize the gic cpu and distributor interfaces */ 189 plat_arm_gic_driver_init(); 190 plat_arm_gic_init(); 191 } 192 193 void bl31_plat_runtime_setup(void) 194 { 195 #if ZYNQMP_WDT_RESTART 196 uint64_t flags = 0; 197 uint64_t rc; 198 199 set_interrupt_rm_flag(flags, NON_SECURE); 200 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 201 rdo_el3_interrupt_handler, flags); 202 if (rc) { 203 panic(); 204 } 205 #endif 206 207 custom_runtime_setup(); 208 } 209 210 /* 211 * Perform the very early platform specific architectural setup here. 212 */ 213 void bl31_plat_arch_setup(void) 214 { 215 plat_arm_interconnect_init(); 216 plat_arm_interconnect_enter_coherency(); 217 218 const mmap_region_t bl_regions[] = { 219 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 220 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 221 MT_MEMORY | MT_RW | MT_NS), 222 #endif 223 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 224 MT_MEMORY | MT_RW | MT_SECURE), 225 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 226 MT_CODE | MT_SECURE), 227 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 228 MT_RO_DATA | MT_SECURE), 229 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 230 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 231 MT_DEVICE | MT_RW | MT_SECURE), 232 {0} 233 }; 234 235 custom_mmap_add(); 236 237 setup_page_tables(bl_regions, plat_get_mmap()); 238 enable_mmu(0); 239 } 240