1# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 2# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 3# Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. 4# 5# SPDX-License-Identifier: BSD-3-Clause 6 7PLAT_PATH := plat/xilinx/versal_net 8 9override PROGRAMMABLE_RESET_ADDRESS := 1 10PSCI_EXTENDED_STATE_ID := 1 11SEPARATE_CODE_AND_RODATA := 1 12override RESET_TO_BL31 := 1 13PL011_GENERIC_UART := 1 14GIC_ENABLE_V4_EXTN := 0 15GICV3_SUPPORT_GIC600 := 1 16TFA_NO_PM := 0 17 18override CTX_INCLUDE_AARCH32_REGS := 0 19 20ifdef TFA_NO_PM 21 $(eval $(call add_define,TFA_NO_PM)) 22endif 23 24ifdef VERSAL_NET_ATF_MEM_BASE 25 $(eval $(call add_define,VERSAL_NET_ATF_MEM_BASE)) 26 27 ifndef VERSAL_NET_ATF_MEM_SIZE 28 $(error "VERSAL_NET_ATF_BASE defined without VERSAL_NET_ATF_SIZE") 29 endif 30 $(eval $(call add_define,VERSAL_NET_ATF_MEM_SIZE)) 31 32 ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE 33 $(eval $(call add_define,VERSAL_NET_ATF_MEM_PROGBITS_SIZE)) 34 endif 35endif 36 37ifdef VERSAL_NET_BL32_MEM_BASE 38 $(eval $(call add_define,VERSAL_NET_BL32_MEM_BASE)) 39 40 ifndef VERSAL_NET_BL32_MEM_SIZE 41 $(error "VERSAL_NET_BL32_BASE defined without VERSAL_NET_BL32_SIZE") 42 endif 43 $(eval $(call add_define,VERSAL_NET_BL32_MEM_SIZE)) 44endif 45 46USE_COHERENT_MEM := 0 47HW_ASSISTED_COHERENCY := 1 48 49VERSAL_NET_CONSOLE ?= pl011 50$(eval $(call add_define_val,VERSAL_NET_CONSOLE,VERSAL_NET_CONSOLE_ID_${VERSAL_NET_CONSOLE})) 51 52PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ 53 -Iplat/xilinx/common/include/ \ 54 -Iplat/xilinx/common/ipi_mailbox_service/ \ 55 -I${PLAT_PATH}/include/ \ 56 -Iplat/xilinx/versal/pm_service/ 57 58# Include GICv3 driver files 59include drivers/arm/gic/v3/gicv3.mk 60include lib/xlat_tables_v2/xlat_tables.mk 61include lib/libfdt/libfdt.mk 62 63PLAT_BL_COMMON_SOURCES := \ 64 drivers/delay_timer/delay_timer.c \ 65 drivers/delay_timer/generic_delay_timer.c \ 66 ${GICV3_SOURCES} \ 67 drivers/arm/pl011/aarch64/pl011_console.S \ 68 plat/arm/common/arm_common.c \ 69 plat/common/plat_gicv3.c \ 70 ${PLAT_PATH}/aarch64/versal_net_helpers.S \ 71 ${PLAT_PATH}/aarch64/versal_net_common.c 72 73BL31_SOURCES += drivers/arm/cci/cci.c \ 74 lib/cpus/aarch64/cortex_a78_ae.S \ 75 lib/cpus/aarch64/cortex_a78.S \ 76 plat/common/plat_psci_common.c 77ifeq ($(TFA_NO_PM), 0) 78BL31_SOURCES += plat/xilinx/versal/pm_service/pm_api_sys.c \ 79 plat/xilinx/common/pm_service/pm_ipi.c \ 80 ${PLAT_PATH}/plat_psci_pm.c \ 81 plat/xilinx/versal/pm_service/pm_svc_main.c \ 82 ${PLAT_PATH}/pm_service/pm_client.c \ 83 ${PLAT_PATH}/versal_net_ipi.c 84else 85BL31_SOURCES += ${PLAT_PATH}/plat_psci.c 86endif 87BL31_SOURCES += plat/xilinx/common/plat_startup.c \ 88 plat/xilinx/common/ipi.c \ 89 plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ 90 ${PLAT_PATH}/bl31_versal_net_setup.c \ 91 ${PLAT_PATH}/plat_topology.c \ 92 common/fdt_fixup.c \ 93 ${LIBFDT_SRCS} \ 94 ${PLAT_PATH}/sip_svc_setup.c \ 95 ${PLAT_PATH}/versal_net_gicv3.c \ 96 ${XLAT_TABLES_LIB_SRCS} 97