1# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 2# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 3# Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 4# 5# SPDX-License-Identifier: BSD-3-Clause 6 7PLAT_PATH := plat/xilinx/versal_net 8 9# A78 Erratum for SoC 10ERRATA_A78_AE_1941500 := 1 11ERRATA_A78_AE_1951502 := 1 12ERRATA_A78_AE_2376748 := 1 13ERRATA_A78_AE_2395408 := 1 14 15override PROGRAMMABLE_RESET_ADDRESS := 1 16PSCI_EXTENDED_STATE_ID := 1 17SEPARATE_CODE_AND_RODATA := 1 18override RESET_TO_BL31 := 1 19PL011_GENERIC_UART := 1 20IPI_CRC_CHECK := 0 21GIC_ENABLE_V4_EXTN := 0 22GICV3_SUPPORT_GIC600 := 1 23TFA_NO_PM := 0 24CPU_PWRDWN_SGI ?= 6 25$(eval $(call add_define_val,CPU_PWR_DOWN_REQ_INTR,ARM_IRQ_SEC_SGI_${CPU_PWRDWN_SGI})) 26 27override CTX_INCLUDE_AARCH32_REGS := 0 28 29ifdef TFA_NO_PM 30 $(eval $(call add_define,TFA_NO_PM)) 31endif 32 33ifdef VERSAL_NET_ATF_MEM_BASE 34 $(eval $(call add_define,VERSAL_NET_ATF_MEM_BASE)) 35 36 ifndef VERSAL_NET_ATF_MEM_SIZE 37 $(error "VERSAL_NET_ATF_MEM_BASE defined without VERSAL_NET_ATF_MEM_SIZE") 38 endif 39 $(eval $(call add_define,VERSAL_NET_ATF_MEM_SIZE)) 40 41 ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE 42 $(eval $(call add_define,VERSAL_NET_ATF_MEM_PROGBITS_SIZE)) 43 endif 44endif 45 46ifdef VERSAL_NET_BL32_MEM_BASE 47 $(eval $(call add_define,VERSAL_NET_BL32_MEM_BASE)) 48 49 ifndef VERSAL_NET_BL32_MEM_SIZE 50 $(error "VERSAL_NET_BL32_MEM_BASE defined without VERSAL_NET_BL32_MEM_SIZE") 51 endif 52 $(eval $(call add_define,VERSAL_NET_BL32_MEM_SIZE)) 53endif 54 55ifdef IPI_CRC_CHECK 56 $(eval $(call add_define,IPI_CRC_CHECK)) 57endif 58 59USE_COHERENT_MEM := 0 60HW_ASSISTED_COHERENCY := 1 61 62VERSAL_NET_CONSOLE ?= pl011 63ifeq (${VERSAL_NET_CONSOLE}, $(filter ${VERSAL_NET_CONSOLE},pl011 pl011_0 pl011_1 dcc dtb none)) 64else 65 $(error Please define VERSAL_NET_CONSOLE) 66endif 67 68$(eval $(call add_define_val,VERSAL_NET_CONSOLE,VERSAL_NET_CONSOLE_ID_${VERSAL_NET_CONSOLE})) 69 70ifdef XILINX_OF_BOARD_DTB_ADDR 71XLNX_DT_CFG := 1 72$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR)) 73else 74XLNX_DT_CFG := 0 75endif 76$(eval $(call add_define,XLNX_DT_CFG)) 77 78# Runtime console in default console in DEBUG build 79ifeq ($(DEBUG), 1) 80CONSOLE_RUNTIME ?= pl011 81endif 82 83# Runtime console 84ifdef CONSOLE_RUNTIME 85ifeq (${CONSOLE_RUNTIME}, $(filter ${CONSOLE_RUNTIME},pl011 pl011_0 pl011_1 dcc dtb)) 86$(eval $(call add_define_val,CONSOLE_RUNTIME,RT_CONSOLE_ID_${CONSOLE_RUNTIME})) 87else 88$(error "Please define CONSOLE_RUNTIME") 89endif 90endif 91 92# enable assert() for release/debug builds 93ENABLE_ASSERTIONS := 1 94 95PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ 96 -Iplat/xilinx/common/include/ \ 97 -Iplat/xilinx/common/ipi_mailbox_service/ \ 98 -I${PLAT_PATH}/include/ \ 99 -Iplat/xilinx/versal/pm_service/ 100 101# Include GICv3 driver files 102include drivers/arm/gic/v3/gicv3.mk 103include lib/xlat_tables_v2/xlat_tables.mk 104include lib/libfdt/libfdt.mk 105 106PLAT_BL_COMMON_SOURCES := \ 107 drivers/arm/dcc/dcc_console.c \ 108 drivers/delay_timer/delay_timer.c \ 109 drivers/delay_timer/generic_delay_timer.c \ 110 ${GICV3_SOURCES} \ 111 drivers/arm/pl011/aarch64/pl011_console.S \ 112 plat/common/aarch64/crash_console_helpers.S \ 113 plat/arm/common/arm_common.c \ 114 plat/common/plat_gicv3.c \ 115 ${PLAT_PATH}/aarch64/versal_net_helpers.S \ 116 ${PLAT_PATH}/aarch64/versal_net_common.c \ 117 ${PLAT_PATH}/plat_topology.c \ 118 ${XLAT_TABLES_LIB_SRCS} 119 120BL31_SOURCES += drivers/arm/cci/cci.c \ 121 lib/cpus/aarch64/cortex_a78_ae.S \ 122 lib/cpus/aarch64/cortex_a78.S \ 123 plat/common/plat_psci_common.c 124ifeq ($(TFA_NO_PM), 0) 125BL31_SOURCES += plat/xilinx/common/pm_service/pm_api_sys.c \ 126 plat/xilinx/common/pm_service/pm_ipi.c \ 127 ${PLAT_PATH}/plat_psci_pm.c \ 128 plat/xilinx/common/pm_service/pm_svc_main.c \ 129 ${PLAT_PATH}/pm_service/pm_client.c \ 130 ${PLAT_PATH}/versal_net_ipi.c 131else 132BL31_SOURCES += ${PLAT_PATH}/plat_psci.c 133endif 134BL31_SOURCES += plat/xilinx/common/plat_fdt.c \ 135 plat/xilinx/common/plat_startup.c \ 136 plat/xilinx/common/plat_console.c \ 137 plat/xilinx/common/plat_clkfunc.c \ 138 plat/xilinx/common/ipi.c \ 139 plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \ 140 plat/xilinx/common/versal.c \ 141 ${PLAT_PATH}/bl31_versal_net_setup.c \ 142 common/fdt_fixup.c \ 143 common/fdt_wrappers.c \ 144 plat/arm/common/arm_gicv3.c \ 145 ${LIBFDT_SRCS} \ 146 ${PLAT_PATH}/sip_svc_setup.c \ 147 ${XLAT_TABLES_LIB_SRCS} 148