1*1d333e69SMichal Simek# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 2*1d333e69SMichal Simek# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 3*1d333e69SMichal Simek# Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. 4*1d333e69SMichal Simek# 5*1d333e69SMichal Simek# SPDX-License-Identifier: BSD-3-Clause 6*1d333e69SMichal Simek 7*1d333e69SMichal SimekPLAT_PATH := plat/xilinx/versal_net 8*1d333e69SMichal Simek 9*1d333e69SMichal Simekoverride PROGRAMMABLE_RESET_ADDRESS := 1 10*1d333e69SMichal SimekPSCI_EXTENDED_STATE_ID := 1 11*1d333e69SMichal SimekSEPARATE_CODE_AND_RODATA := 1 12*1d333e69SMichal Simekoverride RESET_TO_BL31 := 1 13*1d333e69SMichal SimekPL011_GENERIC_UART := 1 14*1d333e69SMichal SimekGIC_ENABLE_V4_EXTN := 0 15*1d333e69SMichal SimekGICV3_SUPPORT_GIC600 := 1 16*1d333e69SMichal Simek 17*1d333e69SMichal Simekoverride CTX_INCLUDE_AARCH32_REGS := 0 18*1d333e69SMichal Simek 19*1d333e69SMichal Simekifdef VERSAL_NET_ATF_MEM_BASE 20*1d333e69SMichal Simek $(eval $(call add_define,VERSAL_NET_ATF_MEM_BASE)) 21*1d333e69SMichal Simek 22*1d333e69SMichal Simek ifndef VERSAL_NET_ATF_MEM_SIZE 23*1d333e69SMichal Simek $(error "VERSAL_NET_ATF_BASE defined without VERSAL_NET_ATF_SIZE") 24*1d333e69SMichal Simek endif 25*1d333e69SMichal Simek $(eval $(call add_define,VERSAL_NET_ATF_MEM_SIZE)) 26*1d333e69SMichal Simek 27*1d333e69SMichal Simek ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE 28*1d333e69SMichal Simek $(eval $(call add_define,VERSAL_NET_ATF_MEM_PROGBITS_SIZE)) 29*1d333e69SMichal Simek endif 30*1d333e69SMichal Simekendif 31*1d333e69SMichal Simek 32*1d333e69SMichal Simekifdef VERSAL_NET_BL32_MEM_BASE 33*1d333e69SMichal Simek $(eval $(call add_define,VERSAL_NET_BL32_MEM_BASE)) 34*1d333e69SMichal Simek 35*1d333e69SMichal Simek ifndef VERSAL_NET_BL32_MEM_SIZE 36*1d333e69SMichal Simek $(error "VERSAL_NET_BL32_BASE defined without VERSAL_NET_BL32_SIZE") 37*1d333e69SMichal Simek endif 38*1d333e69SMichal Simek $(eval $(call add_define,VERSAL_NET_BL32_MEM_SIZE)) 39*1d333e69SMichal Simekendif 40*1d333e69SMichal Simek 41*1d333e69SMichal SimekUSE_COHERENT_MEM := 0 42*1d333e69SMichal SimekHW_ASSISTED_COHERENCY := 1 43*1d333e69SMichal Simek 44*1d333e69SMichal SimekVERSAL_NET_CONSOLE ?= pl011 45*1d333e69SMichal Simek$(eval $(call add_define_val,VERSAL_NET_CONSOLE,VERSAL_NET_CONSOLE_ID_${VERSAL_NET_CONSOLE})) 46*1d333e69SMichal Simek 47*1d333e69SMichal SimekPLAT_INCLUDES := -Iinclude/plat/arm/common/ \ 48*1d333e69SMichal Simek -Iplat/xilinx/common/include/ \ 49*1d333e69SMichal Simek -I${PLAT_PATH}/include/ 50*1d333e69SMichal Simek 51*1d333e69SMichal Simek# Include GICv3 driver files 52*1d333e69SMichal Simekinclude drivers/arm/gic/v3/gicv3.mk 53*1d333e69SMichal Simekinclude lib/xlat_tables_v2/xlat_tables.mk 54*1d333e69SMichal Simekinclude lib/libfdt/libfdt.mk 55*1d333e69SMichal Simek 56*1d333e69SMichal SimekPLAT_BL_COMMON_SOURCES := \ 57*1d333e69SMichal Simek drivers/delay_timer/delay_timer.c \ 58*1d333e69SMichal Simek drivers/delay_timer/generic_delay_timer.c \ 59*1d333e69SMichal Simek ${GICV3_SOURCES} \ 60*1d333e69SMichal Simek drivers/arm/pl011/aarch64/pl011_console.S \ 61*1d333e69SMichal Simek plat/arm/common/arm_common.c \ 62*1d333e69SMichal Simek plat/common/plat_gicv3.c \ 63*1d333e69SMichal Simek ${PLAT_PATH}/aarch64/versal_net_helpers.S \ 64*1d333e69SMichal Simek ${PLAT_PATH}/aarch64/versal_net_common.c 65*1d333e69SMichal Simek 66*1d333e69SMichal SimekBL31_SOURCES += drivers/arm/cci/cci.c \ 67*1d333e69SMichal Simek lib/cpus/aarch64/cortex_a78_ae.S \ 68*1d333e69SMichal Simek lib/cpus/aarch64/cortex_a78.S \ 69*1d333e69SMichal Simek plat/common/plat_psci_common.c \ 70*1d333e69SMichal Simek ${PLAT_PATH}/plat_psci.c \ 71*1d333e69SMichal Simek plat/xilinx/common/plat_startup.c \ 72*1d333e69SMichal Simek ${PLAT_PATH}/bl31_versal_net_setup.c \ 73*1d333e69SMichal Simek ${PLAT_PATH}/plat_topology.c \ 74*1d333e69SMichal Simek common/fdt_fixup.c \ 75*1d333e69SMichal Simek ${LIBFDT_SRCS} \ 76*1d333e69SMichal Simek ${PLAT_PATH}/sip_svc_setup.c \ 77*1d333e69SMichal Simek ${PLAT_PATH}/versal_net_gicv3.c \ 78*1d333e69SMichal Simek ${XLAT_TABLES_LIB_SRCS} 79