1*1d333e69SMichal Simek /* 2*1d333e69SMichal Simek * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*1d333e69SMichal Simek * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4*1d333e69SMichal Simek * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. 5*1d333e69SMichal Simek * 6*1d333e69SMichal Simek * SPDX-License-Identifier: BSD-3-Clause 7*1d333e69SMichal Simek */ 8*1d333e69SMichal Simek 9*1d333e69SMichal Simek #include <common/debug.h> 10*1d333e69SMichal Simek #include <plat/common/platform.h> 11*1d333e69SMichal Simek 12*1d333e69SMichal Simek #include <plat_private.h> 13*1d333e69SMichal Simek #include <platform_def.h> 14*1d333e69SMichal Simek 15*1d333e69SMichal Simek static const uint8_t plat_power_domain_tree_desc[] = { 16*1d333e69SMichal Simek /* Number of root nodes */ 17*1d333e69SMichal Simek 1, 18*1d333e69SMichal Simek /* Number of clusters */ 19*1d333e69SMichal Simek PLATFORM_CLUSTER_COUNT, 20*1d333e69SMichal Simek /* Number of children for the first cluster node */ 21*1d333e69SMichal Simek PLATFORM_CORE_COUNT_PER_CLUSTER, 22*1d333e69SMichal Simek /* Number of children for the second cluster node */ 23*1d333e69SMichal Simek PLATFORM_CORE_COUNT_PER_CLUSTER, 24*1d333e69SMichal Simek /* Number of children for the third cluster node */ 25*1d333e69SMichal Simek PLATFORM_CORE_COUNT_PER_CLUSTER, 26*1d333e69SMichal Simek /* Number of children for the fourth cluster node */ 27*1d333e69SMichal Simek PLATFORM_CORE_COUNT_PER_CLUSTER, 28*1d333e69SMichal Simek }; 29*1d333e69SMichal Simek 30*1d333e69SMichal Simek const uint8_t *plat_get_power_domain_tree_desc(void) 31*1d333e69SMichal Simek { 32*1d333e69SMichal Simek return plat_power_domain_tree_desc; 33*1d333e69SMichal Simek } 34*1d333e69SMichal Simek 35*1d333e69SMichal Simek /******************************************************************************* 36*1d333e69SMichal Simek * This function implements a part of the critical interface between the psci 37*1d333e69SMichal Simek * generic layer and the platform that allows the former to query the platform 38*1d333e69SMichal Simek * to convert an MPIDR to a unique linear index. An error code (-1) is returned 39*1d333e69SMichal Simek * in case the MPIDR is invalid. 40*1d333e69SMichal Simek ******************************************************************************/ 41*1d333e69SMichal Simek int32_t plat_core_pos_by_mpidr(u_register_t mpidr) 42*1d333e69SMichal Simek { 43*1d333e69SMichal Simek uint32_t cluster_id, cpu_id; 44*1d333e69SMichal Simek 45*1d333e69SMichal Simek mpidr &= MPIDR_AFFINITY_MASK; 46*1d333e69SMichal Simek 47*1d333e69SMichal Simek cluster_id = MPIDR_AFFLVL2_VAL(mpidr); 48*1d333e69SMichal Simek cpu_id = MPIDR_AFFLVL1_VAL(mpidr); 49*1d333e69SMichal Simek 50*1d333e69SMichal Simek if (cluster_id >= PLATFORM_CLUSTER_COUNT) { 51*1d333e69SMichal Simek return -3; 52*1d333e69SMichal Simek } 53*1d333e69SMichal Simek 54*1d333e69SMichal Simek /* 55*1d333e69SMichal Simek * Validate cpu_id by checking whether it represents a CPU in 56*1d333e69SMichal Simek * one of the two clusters present on the platform. 57*1d333e69SMichal Simek */ 58*1d333e69SMichal Simek if (cpu_id >= PLATFORM_CORE_COUNT_PER_CLUSTER) { 59*1d333e69SMichal Simek return -1; 60*1d333e69SMichal Simek } 61*1d333e69SMichal Simek 62*1d333e69SMichal Simek return (cpu_id + (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER)); 63*1d333e69SMichal Simek } 64