1 /* 2 * Copyright (c) 2022, Xilinx, Inc. All rights reserved. 3 * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 10 #include <common/debug.h> 11 #include <lib/mmio.h> 12 #include <lib/psci/psci.h> 13 #include <plat/arm/common/plat_arm.h> 14 #include <plat/common/platform.h> 15 #include <plat_arm.h> 16 17 #include <plat_private.h> 18 #include "pm_api_sys.h" 19 #include "pm_client.h" 20 #include <pm_common.h> 21 #include "pm_svc_main.h" 22 #include "versal_net_def.h" 23 24 static uintptr_t versal_net_sec_entry; 25 26 static int32_t versal_net_pwr_domain_on(u_register_t mpidr) 27 { 28 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 29 const struct pm_proc *proc; 30 31 VERBOSE("%s: mpidr: 0x%lx, cpuid: %x\n", 32 __func__, mpidr, cpu_id); 33 34 if (cpu_id == -1) { 35 return PSCI_E_INTERN_FAIL; 36 } 37 38 proc = pm_get_proc(cpu_id); 39 if (!proc) { 40 return PSCI_E_INTERN_FAIL; 41 } 42 43 pm_req_wakeup(proc->node_id, (versal_net_sec_entry & 0xFFFFFFFFU) | 0x1U, 44 versal_net_sec_entry >> 32, 0, 0); 45 46 /* Clear power down request */ 47 pm_client_wakeup(proc); 48 49 return PSCI_E_SUCCESS; 50 } 51 52 /** 53 * versal_net_pwr_domain_off() - This function performs actions to turn off core 54 * 55 * @param target_state Targeted state 56 */ 57 static void versal_net_pwr_domain_off(const psci_power_state_t *target_state) 58 { 59 uint32_t cpu_id = plat_my_core_pos(); 60 const struct pm_proc *proc = pm_get_proc(cpu_id); 61 62 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 63 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 64 __func__, i, target_state->pwr_domain_state[i]); 65 } 66 67 /* Prevent interrupts from spuriously waking up this cpu */ 68 plat_versal_net_gic_cpuif_disable(); 69 70 /* 71 * Send request to PMC to power down the appropriate APU CPU 72 * core. 73 * According to PSCI specification, CPU_off function does not 74 * have resume address and CPU core can only be woken up 75 * invoking CPU_on function, during which resume address will 76 * be set. 77 */ 78 pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0, 79 SECURE_FLAG); 80 } 81 82 /** 83 * versal_net_system_reset() - This function sends the reset request 84 * to firmware for the system to reset. This function does not return. 85 */ 86 static void __dead2 versal_net_system_reset(void) 87 { 88 /* Send the system reset request to the PMC */ 89 pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET, 90 pm_get_shutdown_scope(), SECURE_FLAG); 91 92 while (1) { 93 wfi(); 94 } 95 } 96 97 /** 98 * versal_net_pwr_domain_suspend() - This function sends request to PMC to suspend 99 * core. 100 * 101 * @param target_state Targeted state 102 */ 103 static void versal_net_pwr_domain_suspend(const psci_power_state_t *target_state) 104 { 105 uint32_t state; 106 uint32_t cpu_id = plat_my_core_pos(); 107 const struct pm_proc *proc = pm_get_proc(cpu_id); 108 109 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { 110 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 111 __func__, i, target_state->pwr_domain_state[i]); 112 } 113 114 plat_versal_net_gic_cpuif_disable(); 115 116 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 117 plat_versal_net_gic_save(); 118 } 119 120 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? 121 PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE; 122 123 /* Send request to PMC to suspend this core */ 124 pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_net_sec_entry, 125 SECURE_FLAG); 126 127 /* TODO: disable coherency */ 128 } 129 130 static void versal_net_pwr_domain_on_finish(const psci_power_state_t *target_state) 131 { 132 (void)target_state; 133 134 /* Enable the gic cpu interface */ 135 plat_versal_net_gic_pcpu_init(); 136 137 /* Program the gic per-cpu distributor or re-distributor interface */ 138 plat_versal_net_gic_cpuif_enable(); 139 } 140 141 /** 142 * versal_net_pwr_domain_suspend_finish() - This function performs actions to finish 143 * suspend procedure. 144 * 145 * @param target_state Targeted state 146 */ 147 static void versal_net_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 148 { 149 uint32_t cpu_id = plat_my_core_pos(); 150 const struct pm_proc *proc = pm_get_proc(cpu_id); 151 152 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) 153 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 154 __func__, i, target_state->pwr_domain_state[i]); 155 156 /* Clear the APU power control register for this cpu */ 157 pm_client_wakeup(proc); 158 159 /* TODO: enable coherency */ 160 161 /* APU was turned off, so restore GIC context */ 162 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 163 plat_versal_net_gic_resume(); 164 } 165 166 plat_versal_net_gic_cpuif_enable(); 167 } 168 169 /** 170 * versal_net_system_off() - This function sends the system off request 171 * to firmware. This function does not return. 172 */ 173 static void __dead2 versal_net_system_off(void) 174 { 175 /* Send the power down request to the PMC */ 176 pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN, 177 pm_get_shutdown_scope(), SECURE_FLAG); 178 179 while (1) { 180 wfi(); 181 } 182 } 183 184 /** 185 * versal_net_validate_power_state() - This function ensures that the power state 186 * parameter in request is valid. 187 * 188 * @param power_state Power state of core 189 * @param req_state Requested state 190 * 191 * @return Returns status, either PSCI_E_SUCCESS or reason 192 */ 193 static int32_t versal_net_validate_power_state(unsigned int power_state, 194 psci_power_state_t *req_state) 195 { 196 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); 197 198 int32_t pstate = psci_get_pstate_type(power_state); 199 200 assert(req_state); 201 202 /* Sanity check the requested state */ 203 if (pstate == PSTATE_TYPE_STANDBY) { 204 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; 205 } else { 206 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 207 } 208 209 /* We expect the 'state id' to be zero */ 210 if (psci_get_pstate_id(power_state)) { 211 return PSCI_E_INVALID_PARAMS; 212 } 213 214 return PSCI_E_SUCCESS; 215 } 216 217 /** 218 * versal_net_get_sys_suspend_power_state() - Get power state for system suspend 219 * 220 * @param req_state Requested state 221 */ 222 static void versal_net_get_sys_suspend_power_state(psci_power_state_t *req_state) 223 { 224 uint64_t i; 225 226 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) 227 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 228 } 229 230 static const struct plat_psci_ops versal_net_nopmc_psci_ops = { 231 .pwr_domain_on = versal_net_pwr_domain_on, 232 .pwr_domain_off = versal_net_pwr_domain_off, 233 .pwr_domain_on_finish = versal_net_pwr_domain_on_finish, 234 .pwr_domain_suspend = versal_net_pwr_domain_suspend, 235 .pwr_domain_suspend_finish = versal_net_pwr_domain_suspend_finish, 236 .system_off = versal_net_system_off, 237 .system_reset = versal_net_system_reset, 238 .validate_power_state = versal_net_validate_power_state, 239 .get_sys_suspend_power_state = versal_net_get_sys_suspend_power_state, 240 }; 241 242 /******************************************************************************* 243 * Export the platform specific power ops. 244 ******************************************************************************/ 245 int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint, 246 const struct plat_psci_ops **psci_ops) 247 { 248 versal_net_sec_entry = sec_entrypoint; 249 250 VERBOSE("Setting up entry point %lx\n", versal_net_sec_entry); 251 252 *psci_ops = &versal_net_nopmc_psci_ops; 253 254 return 0; 255 } 256 257 int32_t sip_svc_setup_init(void) 258 { 259 return pm_setup(); 260 } 261 262 uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, 263 void *cookie, void *handle, uint64_t flags) 264 { 265 return pm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 266 } 267