1 /* 2 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 11 #include <common/debug.h> 12 #include <common/runtime_svc.h> 13 #include <lib/mmio.h> 14 #include <lib/psci/psci.h> 15 #include <plat/arm/common/plat_arm.h> 16 #include <plat/common/platform.h> 17 #include <plat_arm.h> 18 19 #include <plat_private.h> 20 21 #define PM_RET_ERROR_NOFEATURE U(19) 22 23 #define PM_IOCTL 34U 24 25 static uintptr_t versal_net_sec_entry; 26 27 static void zynqmp_cpu_standby(plat_local_state_t cpu_state) 28 { 29 dsb(); 30 wfi(); 31 } 32 33 static int32_t zynqmp_nopmu_pwr_domain_on(u_register_t mpidr) 34 { 35 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 36 uint32_t cpu = cpu_id % PLATFORM_CORE_COUNT_PER_CLUSTER; 37 uint32_t cluster = cpu_id / PLATFORM_CORE_COUNT_PER_CLUSTER; 38 uintptr_t apu_cluster_base = 0, apu_pcli_base, apu_pcli_cluster = 0; 39 uintptr_t rst_apu_cluster = PSX_CRF + RST_APU0_OFFSET + (cluster * 0x4); 40 41 VERBOSE("%s: mpidr: 0x%lx, cpuid: %x, cpu: %x, cluster: %x\n", 42 __func__, mpidr, cpu_id, cpu, cluster); 43 44 if (cpu_id == -1) { 45 return PSCI_E_INTERN_FAIL; 46 } 47 48 if (platform_id == VERSAL_NET_SPP && cluster > 1) { 49 panic(); 50 } 51 52 if (cluster > 3) { 53 panic(); 54 } 55 56 apu_pcli_cluster = APU_PCLI + APU_PCLI_CLUSTER_OFFSET + (cluster * APU_PCLI_CLUSTER_STEP); 57 apu_cluster_base = APU_CLUSTER0 + (cluster * APU_CLUSTER_STEP); 58 59 /* Enable clock */ 60 mmio_setbits_32(PSX_CRF + ACPU0_CLK_CTRL + (cluster * 0x4), ACPU_CLK_CTRL_CLKACT); 61 62 /* Enable cluster states */ 63 mmio_setbits_32(apu_pcli_cluster + PCLI_PSTATE_OFFSET, PCLI_PSTATE_VAL_SET); 64 mmio_setbits_32(apu_pcli_cluster + PCLI_PREQ_OFFSET, PREQ_CHANGE_REQUEST); 65 66 /* assert core reset */ 67 mmio_setbits_32(rst_apu_cluster, ((RST_APU_COLD_RESET|RST_APU_WARN_RESET) << cpu)); 68 69 /* program RVBAR */ 70 mmio_write_32(apu_cluster_base + APU_RVBAR_L_0 + (cpu << 3), 71 (uint32_t)versal_net_sec_entry); 72 mmio_write_32(apu_cluster_base + APU_RVBAR_H_0 + (cpu << 3), 73 versal_net_sec_entry >> 32); 74 75 /* de-assert core reset */ 76 mmio_clrbits_32(rst_apu_cluster, ((RST_APU_COLD_RESET|RST_APU_WARN_RESET) << cpu)); 77 78 /* clear cluster resets */ 79 mmio_clrbits_32(rst_apu_cluster, RST_APU_CLUSTER_WARM_RESET); 80 mmio_clrbits_32(rst_apu_cluster, RST_APU_CLUSTER_COLD_RESET); 81 82 apu_pcli_base = APU_PCLI + (APU_PCLI_CPU_STEP * cpu) + 83 (APU_PCLI_CLUSTER_CPU_STEP * cluster); 84 85 mmio_write_32(apu_pcli_base + PCLI_PSTATE_OFFSET, PCLI_PSTATE_VAL_CLEAR); 86 mmio_write_32(apu_pcli_base + PCLI_PREQ_OFFSET, PREQ_CHANGE_REQUEST); 87 88 return PSCI_E_SUCCESS; 89 } 90 91 static void zynqmp_nopmu_pwr_domain_off(const psci_power_state_t *target_state) 92 { 93 } 94 95 static void __dead2 zynqmp_nopmu_system_reset(void) 96 { 97 while (1) 98 wfi(); 99 } 100 101 static int32_t zynqmp_validate_ns_entrypoint(uint64_t ns_entrypoint) 102 { 103 return PSCI_E_SUCCESS; 104 } 105 106 static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state) 107 { 108 } 109 110 static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state) 111 { 112 plat_versal_net_gic_pcpu_init(); 113 plat_versal_net_gic_cpuif_enable(); 114 } 115 116 static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 117 { 118 } 119 120 static void __dead2 zynqmp_system_off(void) 121 { 122 while (1) 123 wfi(); 124 } 125 126 static int32_t zynqmp_validate_power_state(uint32_t power_state, psci_power_state_t *req_state) 127 { 128 return PSCI_E_SUCCESS; 129 } 130 131 static void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state) 132 { 133 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; 134 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; 135 } 136 137 static const struct plat_psci_ops versal_net_nopmc_psci_ops = { 138 .cpu_standby = zynqmp_cpu_standby, 139 .pwr_domain_on = zynqmp_nopmu_pwr_domain_on, 140 .pwr_domain_off = zynqmp_nopmu_pwr_domain_off, 141 .system_reset = zynqmp_nopmu_system_reset, 142 .validate_ns_entrypoint = zynqmp_validate_ns_entrypoint, 143 .pwr_domain_suspend = zynqmp_pwr_domain_suspend, 144 .pwr_domain_on_finish = zynqmp_pwr_domain_on_finish, 145 .pwr_domain_suspend_finish = zynqmp_pwr_domain_suspend_finish, 146 .system_off = zynqmp_system_off, 147 .validate_power_state = zynqmp_validate_power_state, 148 .get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state, 149 }; 150 151 /******************************************************************************* 152 * Export the platform specific power ops. 153 ******************************************************************************/ 154 int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint, 155 const struct plat_psci_ops **psci_ops) 156 { 157 versal_net_sec_entry = sec_entrypoint; 158 159 VERBOSE("Setting up entry point %lx\n", versal_net_sec_entry); 160 161 *psci_ops = &versal_net_nopmc_psci_ops; 162 163 return 0; 164 } 165 166 int sip_svc_setup_init(void) 167 { 168 return 0; 169 } 170 171 static int32_t no_pm_ioctl(uint32_t device_id, uint32_t ioctl_id, 172 uint32_t arg1, uint32_t arg2) 173 { 174 VERBOSE("%s: ioctl_id: %x, arg1: %x\n", __func__, ioctl_id, arg1); 175 if (ioctl_id == IOCTL_OSPI_MUX_SELECT) { 176 mmio_write_32(SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL, arg1); 177 return 0; 178 } 179 return PM_RET_ERROR_NOFEATURE; 180 } 181 182 static uint64_t no_pm_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, 183 uint64_t x4, void *cookie, void *handle, uint64_t flags) 184 { 185 int32_t ret; 186 uint32_t arg[4], api_id; 187 188 arg[0] = (uint32_t)x1; 189 arg[1] = (uint32_t)(x1 >> 32); 190 arg[2] = (uint32_t)x2; 191 arg[3] = (uint32_t)(x2 >> 32); 192 193 api_id = smc_fid & FUNCID_NUM_MASK; 194 VERBOSE("%s: smc_fid: %x, api_id=0x%x\n", __func__, smc_fid, api_id); 195 196 switch (api_id) { 197 case PM_IOCTL: 198 { 199 ret = no_pm_ioctl(arg[0], arg[1], arg[2], arg[3]); 200 SMC_RET1(handle, (uint64_t)ret); 201 } 202 case PM_GET_CHIPID: 203 { 204 uint32_t idcode, version; 205 206 idcode = mmio_read_32(PMC_TAP); 207 version = mmio_read_32(PMC_TAP_VERSION); 208 SMC_RET2(handle, ((uint64_t)idcode << 32), version); 209 } 210 default: 211 WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid); 212 SMC_RET1(handle, SMC_UNK); 213 } 214 } 215 216 uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, 217 void *cookie, void *handle, uint64_t flags) 218 { 219 return no_pm_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 220 } 221