1 /* 2 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 11 #include <common/debug.h> 12 #include <common/runtime_svc.h> 13 #include <lib/mmio.h> 14 #include <lib/psci/psci.h> 15 #include <plat/arm/common/plat_arm.h> 16 #include <plat/common/platform.h> 17 #include <plat_arm.h> 18 19 #include <plat_private.h> 20 21 #define FUNCID_MASK U(0xffff) 22 #define PM_RET_ERROR_NOFEATURE U(19) 23 24 #define PM_IOCTL 34U 25 26 static uintptr_t versal_net_sec_entry; 27 28 static void zynqmp_cpu_standby(plat_local_state_t cpu_state) 29 { 30 dsb(); 31 wfi(); 32 } 33 34 static int32_t zynqmp_nopmu_pwr_domain_on(u_register_t mpidr) 35 { 36 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 37 uint32_t cpu = cpu_id % PLATFORM_CORE_COUNT_PER_CLUSTER; 38 uint32_t cluster = cpu_id / PLATFORM_CORE_COUNT_PER_CLUSTER; 39 uintptr_t apu_cluster_base = 0, apu_pcli_base, apu_pcli_cluster = 0; 40 uintptr_t rst_apu_cluster = PSX_CRF + RST_APU0_OFFSET + (cluster * 0x4); 41 42 VERBOSE("%s: mpidr: 0x%lx, cpuid: %x, cpu: %x, cluster: %x\n", 43 __func__, mpidr, cpu_id, cpu, cluster); 44 45 if (cpu_id == -1) { 46 return PSCI_E_INTERN_FAIL; 47 } 48 49 if (platform_id == VERSAL_NET_SPP && cluster > 1) { 50 panic(); 51 } 52 53 if (cluster > 3) { 54 panic(); 55 } 56 57 apu_pcli_cluster = APU_PCLI + APU_PCLI_CLUSTER_OFFSET + (cluster * APU_PCLI_CLUSTER_STEP); 58 apu_cluster_base = APU_CLUSTER0 + (cluster * APU_CLUSTER_STEP); 59 60 /* Enable clock */ 61 mmio_setbits_32(PSX_CRF + ACPU0_CLK_CTRL + (cluster * 0x4), ACPU_CLK_CTRL_CLKACT); 62 63 /* Enable cluster states */ 64 mmio_setbits_32(apu_pcli_cluster + PCLI_PSTATE_OFFSET, PCLI_PSTATE_VAL_SET); 65 mmio_setbits_32(apu_pcli_cluster + PCLI_PREQ_OFFSET, PREQ_CHANGE_REQUEST); 66 67 /* assert core reset */ 68 mmio_setbits_32(rst_apu_cluster, ((RST_APU_COLD_RESET|RST_APU_WARN_RESET) << cpu)); 69 70 /* program RVBAR */ 71 mmio_write_32(apu_cluster_base + APU_RVBAR_L_0 + (cpu << 3), 72 (uint32_t)versal_net_sec_entry); 73 mmio_write_32(apu_cluster_base + APU_RVBAR_H_0 + (cpu << 3), 74 versal_net_sec_entry >> 32); 75 76 /* de-assert core reset */ 77 mmio_clrbits_32(rst_apu_cluster, ((RST_APU_COLD_RESET|RST_APU_WARN_RESET) << cpu)); 78 79 /* clear cluster resets */ 80 mmio_clrbits_32(rst_apu_cluster, RST_APU_CLUSTER_WARM_RESET); 81 mmio_clrbits_32(rst_apu_cluster, RST_APU_CLUSTER_COLD_RESET); 82 83 apu_pcli_base = APU_PCLI + (APU_PCLI_CPU_STEP * cpu) + 84 (APU_PCLI_CLUSTER_CPU_STEP * cluster); 85 86 mmio_write_32(apu_pcli_base + PCLI_PSTATE_OFFSET, PCLI_PSTATE_VAL_CLEAR); 87 mmio_write_32(apu_pcli_base + PCLI_PREQ_OFFSET, PREQ_CHANGE_REQUEST); 88 89 return PSCI_E_SUCCESS; 90 } 91 92 static void zynqmp_nopmu_pwr_domain_off(const psci_power_state_t *target_state) 93 { 94 } 95 96 static void __dead2 zynqmp_nopmu_system_reset(void) 97 { 98 while (1) 99 wfi(); 100 } 101 102 static int32_t zynqmp_validate_ns_entrypoint(uint64_t ns_entrypoint) 103 { 104 return PSCI_E_SUCCESS; 105 } 106 107 static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state) 108 { 109 } 110 111 static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state) 112 { 113 plat_versal_net_gic_pcpu_init(); 114 plat_versal_net_gic_cpuif_enable(); 115 } 116 117 static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 118 { 119 } 120 121 static void __dead2 zynqmp_system_off(void) 122 { 123 while (1) 124 wfi(); 125 } 126 127 static int32_t zynqmp_validate_power_state(uint32_t power_state, psci_power_state_t *req_state) 128 { 129 return PSCI_E_SUCCESS; 130 } 131 132 static void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state) 133 { 134 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; 135 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; 136 } 137 138 static const struct plat_psci_ops versal_net_nopmc_psci_ops = { 139 .cpu_standby = zynqmp_cpu_standby, 140 .pwr_domain_on = zynqmp_nopmu_pwr_domain_on, 141 .pwr_domain_off = zynqmp_nopmu_pwr_domain_off, 142 .system_reset = zynqmp_nopmu_system_reset, 143 .validate_ns_entrypoint = zynqmp_validate_ns_entrypoint, 144 .pwr_domain_suspend = zynqmp_pwr_domain_suspend, 145 .pwr_domain_on_finish = zynqmp_pwr_domain_on_finish, 146 .pwr_domain_suspend_finish = zynqmp_pwr_domain_suspend_finish, 147 .system_off = zynqmp_system_off, 148 .validate_power_state = zynqmp_validate_power_state, 149 .get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state, 150 }; 151 152 /******************************************************************************* 153 * Export the platform specific power ops. 154 ******************************************************************************/ 155 int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint, 156 const struct plat_psci_ops **psci_ops) 157 { 158 versal_net_sec_entry = sec_entrypoint; 159 160 VERBOSE("Setting up entry point %lx\n", versal_net_sec_entry); 161 162 *psci_ops = &versal_net_nopmc_psci_ops; 163 164 return 0; 165 } 166 167 int sip_svc_setup_init(void) 168 { 169 return 0; 170 } 171 172 static int32_t no_pm_ioctl(uint32_t device_id, uint32_t ioctl_id, 173 uint32_t arg1, uint32_t arg2) 174 { 175 VERBOSE("%s: ioctl_id: %x, arg1: %x\n", __func__, ioctl_id, arg1); 176 if (ioctl_id == IOCTL_OSPI_MUX_SELECT) { 177 mmio_write_32(SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL, arg1); 178 return 0; 179 } 180 return PM_RET_ERROR_NOFEATURE; 181 } 182 183 static uint64_t no_pm_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, 184 uint64_t x4, void *cookie, void *handle, uint64_t flags) 185 { 186 int32_t ret; 187 uint32_t arg[4], api_id; 188 189 arg[0] = (uint32_t)x1; 190 arg[1] = (uint32_t)(x1 >> 32); 191 arg[2] = (uint32_t)x2; 192 arg[3] = (uint32_t)(x2 >> 32); 193 194 api_id = smc_fid & FUNCID_NUM_MASK; 195 VERBOSE("%s: smc_fid: %x, api_id=0x%x\n", __func__, smc_fid, api_id); 196 197 switch (smc_fid & FUNCID_MASK) { 198 case PM_IOCTL: 199 { 200 ret = no_pm_ioctl(arg[0], arg[1], arg[2], arg[3]); 201 SMC_RET1(handle, (uint64_t)ret); 202 } 203 case PM_GET_CHIPID: 204 { 205 uint32_t idcode, version; 206 207 idcode = mmio_read_32(PMC_TAP); 208 version = mmio_read_32(PMC_TAP_VERSION); 209 SMC_RET2(handle, ((uint64_t)idcode << 32), version); 210 } 211 default: 212 WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid); 213 SMC_RET1(handle, SMC_UNK); 214 } 215 } 216 217 uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, 218 void *cookie, void *handle, uint64_t flags) 219 { 220 return no_pm_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 221 } 222