xref: /rk3399_ARM-atf/plat/xilinx/versal_net/include/versal_net_def.h (revision def661b6ef7f429041be70d7ed0c92399c505abc) 
1 /*
2  * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
3  * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
4  * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #ifndef VERSAL_NET_DEF_H
10 #define VERSAL_NET_DEF_H
11 
12 #include <plat/arm/common/smccc_def.h>
13 #include <plat/common/common_def.h>
14 
15 #define MAX_INTR_EL3			2
16 /* This part is taken from U-Boot project under GPL that's why dual license above */
17 #define __bf_shf(x) (__builtin_ffsll(x) - 1U)
18 #define FIELD_GET(_mask, _reg)						\
19 	({								\
20 		(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask));	\
21 	})
22 
23 /* List all consoles */
24 #define VERSAL_NET_CONSOLE_ID_pl011	U(1)
25 #define VERSAL_NET_CONSOLE_ID_pl011_0	U(1)
26 #define VERSAL_NET_CONSOLE_ID_pl011_1	U(2)
27 
28 #define VERSAL_NET_CONSOLE_IS(con)	(VERSAL_NET_CONSOLE_ID_ ## con == VERSAL_NET_CONSOLE)
29 
30 /* List all platforms */
31 #define VERSAL_NET_SILICON		U(0)
32 #define VERSAL_NET_SPP			U(1)
33 #define VERSAL_NET_EMU			U(2)
34 #define VERSAL_NET_QEMU			U(3)
35 
36 /* For platform detection */
37 #define PMC_TAP				U(0xF11A0000)
38 #define PMC_TAP_VERSION			(PMC_TAP + 0x4U)
39 # define PLATFORM_MASK			GENMASK(27U, 24U)
40 # define PLATFORM_VERSION_MASK		GENMASK(31U, 28U)
41 
42 /* Global timer reset */
43 #define PSX_CRF			U(0xEC200000)
44 #define ACPU0_CLK_CTRL		U(0x10C)
45 #define ACPU_CLK_CTRL_CLKACT	BIT(25)
46 
47 #define RST_APU0_OFFSET		U(0x300)
48 #define RST_APU_COLD_RESET	BIT(0)
49 #define RST_APU_WARN_RESET	BIT(4)
50 #define RST_APU_CLUSTER_COLD_RESET	BIT(8)
51 #define RST_APU_CLUSTER_WARM_RESET	BIT(9)
52 
53 #define PSX_CRF_RST_TIMESTAMP_OFFSET	U(0x33C)
54 
55 #define APU_PCLI			U(0xECB10000)
56 #define APU_PCLI_CPU_STEP		U(0x30)
57 #define APU_PCLI_CLUSTER_CPU_STEP	(4U * APU_PCLI_CPU_STEP)
58 #define APU_PCLI_CLUSTER_OFFSET		U(0x8000)
59 #define APU_PCLI_CLUSTER_STEP		U(0x1000)
60 #define PCLI_PREQ_OFFSET		U(0x4)
61 #define PREQ_CHANGE_REQUEST		BIT(0)
62 #define PCLI_PSTATE_OFFSET		U(0x8)
63 #define PCLI_PSTATE_VAL_SET		U(0x48)
64 #define PCLI_PSTATE_VAL_CLEAR		U(0x38)
65 
66 /* Firmware Image Package */
67 #define VERSAL_NET_PRIMARY_CPU		U(0)
68 
69 #define CORE_0_IEN_POWER_OFFSET			(0x00000018U)
70 #define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id)	(APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \
71 						 (0x30 * cpu_id)))
72 #define APU_PCIL_CORE_X_IEN_POWER_MASK		(0x00000001U)
73 #define CORE_0_IDS_POWER_OFFSET			(0x0000001CU)
74 #define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id)	(APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \
75 						 (0x30 * cpu_id)))
76 #define APU_PCIL_CORE_X_IDS_POWER_MASK		(0x00000001U)
77 #define CORE_PWRDN_EN_BIT_MASK			(0x1U)
78 
79 /*******************************************************************************
80  * memory map related constants
81  ******************************************************************************/
82 /* IPP 1.2/SPP 0.9 mapping */
83 #define DEVICE0_BASE		U(0xE8000000) /* psx, crl, iou */
84 #define DEVICE0_SIZE		U(0x08000000)
85 #define DEVICE1_BASE		U(0xE2000000) /* gic */
86 #define DEVICE1_SIZE		U(0x00800000)
87 #define DEVICE2_BASE		U(0xF1000000) /* uart, pmc_tap */
88 #define DEVICE2_SIZE		U(0x01000000)
89 #define CRF_BASE		U(0xFD1A0000)
90 #define CRF_SIZE		U(0x00600000)
91 #define IPI_BASE		U(0xEB300000)
92 #define IPI_SIZE		U(0x00100000)
93 
94 /* CRL */
95 #define VERSAL_NET_CRL					U(0xEB5E0000)
96 #define VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET	U(0x14C)
97 #define VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET		U(0x348)
98 
99 #define VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT	(1U << 25U)
100 
101 /* IOU SCNTRS */
102 #define VERSAL_NET_IOU_SCNTRS					U(0xEC920000)
103 #define VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET	U(0)
104 #define VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET			U(0x20)
105 
106 #define VERSAL_NET_IOU_SCNTRS_CONTROL_EN	U(1)
107 
108 #define APU_CLUSTER0		U(0xECC00000)
109 #define APU_RVBAR_L_0		U(0x40)
110 #define APU_RVBAR_H_0		U(0x44)
111 #define APU_CLUSTER_STEP	U(0x100000)
112 
113 #define SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL	U(0xF1060504)
114 
115 /*******************************************************************************
116  * IRQ constants
117  ******************************************************************************/
118 #define VERSAL_NET_IRQ_SEC_PHY_TIMER	U(29)
119 
120 /*******************************************************************************
121  * UART related constants
122  ******************************************************************************/
123 #define VERSAL_NET_UART0_BASE		U(0xF1920000)
124 #define VERSAL_NET_UART_BAUDRATE	115200
125 
126 #define VERSAL_NET_UART_BASE		VERSAL_NET_UART0_BASE
127 
128 #define PLAT_VERSAL_NET_CRASH_UART_BASE		VERSAL_NET_UART_BASE
129 #define PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ	VERSAL_NET_UART_CLOCK
130 #define VERSAL_NET_CONSOLE_BAUDRATE		VERSAL_NET_UART_BAUDRATE
131 
132 /*******************************************************************************
133  * IPI registers and bitfields
134  ******************************************************************************/
135 #define IPI0_REG_BASE		(0xEB330000U)
136 #define IPI0_TRIG_BIT		(1 << 2)
137 #define PMC_IPI_TRIG_BIT	(1 << 1)
138 #define IPI1_REG_BASE		(0xEB340000U)
139 #define IPI1_TRIG_BIT		(1 << 3)
140 #define IPI2_REG_BASE		(0xEB350000U)
141 #define IPI2_TRIG_BIT		(1 << 4)
142 #define IPI3_REG_BASE		(0xEB360000U)
143 #define IPI3_TRIG_BIT		(1 << 5)
144 #define IPI4_REG_BASE		(0xEB370000U)
145 #define IPI4_TRIG_BIT		(1 << 6)
146 #define IPI5_REG_BASE		(0xEB380000U)
147 #define IPI5_TRIG_BIT		(1 << 7)
148 
149 /* Processor core device IDs */
150 #define PM_DEV_CLUSTER0_ACPU_0	(0x1810C0AFU)
151 #define PM_DEV_CLUSTER0_ACPU_1	(0x1810C0B0U)
152 #define PM_DEV_CLUSTER0_ACPU_2	(0x1810C0B1U)
153 #define PM_DEV_CLUSTER0_ACPU_3	(0x1810C0B2U)
154 
155 #define PM_DEV_CLUSTER1_ACPU_0	(0x1810C0B3U)
156 #define PM_DEV_CLUSTER1_ACPU_1	(0x1810C0B4U)
157 #define PM_DEV_CLUSTER1_ACPU_2	(0x1810C0B5U)
158 #define PM_DEV_CLUSTER1_ACPU_3	(0x1810C0B6U)
159 
160 #define PM_DEV_CLUSTER2_ACPU_0	(0x1810C0B7U)
161 #define PM_DEV_CLUSTER2_ACPU_1	(0x1810C0B8U)
162 #define PM_DEV_CLUSTER2_ACPU_2	(0x1810C0B9U)
163 #define PM_DEV_CLUSTER2_ACPU_3	(0x1810C0BAU)
164 
165 #define PM_DEV_CLUSTER3_ACPU_0	(0x1810C0BBU)
166 #define PM_DEV_CLUSTER3_ACPU_1	(0x1810C0BCU)
167 #define PM_DEV_CLUSTER3_ACPU_2	(0x1810C0BDU)
168 #define PM_DEV_CLUSTER3_ACPU_3	(0x1810C0BEU)
169 
170 #endif /* VERSAL_NET_DEF_H */
171