1 /* 2 * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef VERSAL_NET_DEF_H 10 #define VERSAL_NET_DEF_H 11 12 #include <plat/arm/common/smccc_def.h> 13 #include <plat/common/common_def.h> 14 15 #define MAX_INTR_EL3 2 16 17 /* List all consoles */ 18 #define VERSAL_NET_CONSOLE_ID_pl011 U(1) 19 #define VERSAL_NET_CONSOLE_ID_pl011_0 U(1) 20 #define VERSAL_NET_CONSOLE_ID_pl011_1 U(2) 21 #define VERSAL_NET_CONSOLE_ID_dcc U(3) 22 #define VERSAL_NET_CONSOLE_ID_dtb U(4) 23 24 #define CONSOLE_IS(con) (VERSAL_NET_CONSOLE_ID_ ## con == VERSAL_NET_CONSOLE) 25 26 /* Runtime console */ 27 #define RT_CONSOLE_ID_pl011 1 28 #define RT_CONSOLE_ID_pl011_0 1 29 #define RT_CONSOLE_ID_pl011_1 2 30 #define RT_CONSOLE_ID_dcc 3 31 #define RT_CONSOLE_ID_dtb 4 32 33 #define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME) 34 35 /* List all platforms */ 36 #define VERSAL_NET_SILICON U(0) 37 #define VERSAL_NET_SPP U(1) 38 #define VERSAL_NET_EMU U(2) 39 #define VERSAL_NET_QEMU U(3) 40 #define VERSAL_NET_QEMU_COSIM U(7) 41 42 /* For platform detection */ 43 #define PMC_TAP U(0xF11A0000) 44 #define PMC_TAP_VERSION (PMC_TAP + 0x4U) 45 # define PLATFORM_MASK GENMASK(27U, 24U) 46 # define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 47 48 /* Global timer reset */ 49 #define PSX_CRF U(0xEC200000) 50 #define ACPU0_CLK_CTRL U(0x10C) 51 #define ACPU_CLK_CTRL_CLKACT BIT(25) 52 53 #define RST_APU0_OFFSET U(0x300) 54 #define RST_APU_COLD_RESET BIT(0) 55 #define RST_APU_WARN_RESET BIT(4) 56 #define RST_APU_CLUSTER_COLD_RESET BIT(8) 57 #define RST_APU_CLUSTER_WARM_RESET BIT(9) 58 59 #define PSX_CRF_RST_TIMESTAMP_OFFSET U(0x33C) 60 61 #define APU_PCLI (0xECB10000ULL) 62 #define APU_PCLI_CPU_STEP (0x30ULL) 63 #define APU_PCLI_CLUSTER_CPU_STEP (4ULL * APU_PCLI_CPU_STEP) 64 #define APU_PCLI_CLUSTER_OFFSET U(0x8000) 65 #define APU_PCLI_CLUSTER_STEP U(0x1000) 66 #define PCLI_PREQ_OFFSET U(0x4) 67 #define PREQ_CHANGE_REQUEST BIT(0) 68 #define PCLI_PSTATE_OFFSET U(0x8) 69 #define PCLI_PSTATE_VAL_SET U(0x48) 70 #define PCLI_PSTATE_VAL_CLEAR U(0x38) 71 72 /* Firmware Image Package */ 73 #define VERSAL_NET_PRIMARY_CPU U(0) 74 75 #define CORE_0_ISR_WAKE_OFFSET (0x00000020ULL) 76 #define APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_WAKE_OFFSET + \ 77 (APU_PCLI_CPU_STEP * (cpu_id)))) 78 #define APU_PCIL_CORE_X_ISR_WAKE_MASK (0x00000001U) 79 #define CORE_0_IEN_WAKE_OFFSET (0x00000028ULL) 80 #define APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_WAKE_OFFSET + \ 81 (APU_PCLI_CPU_STEP * (cpu_id)))) 82 #define APU_PCIL_CORE_X_IEN_WAKE_MASK (0x00000001U) 83 #define CORE_0_IDS_WAKE_OFFSET (0x0000002CULL) 84 #define APU_PCIL_CORE_X_IDS_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_WAKE_OFFSET + \ 85 (APU_PCLI_CPU_STEP * (cpu_id)))) 86 #define APU_PCIL_CORE_X_IDS_WAKE_MASK (0x00000001U) 87 #define CORE_0_ISR_POWER_OFFSET (0x00000010ULL) 88 #define APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_POWER_OFFSET + \ 89 (APU_PCLI_CPU_STEP * (cpu_id)))) 90 #define APU_PCIL_CORE_X_ISR_POWER_MASK U(0x00000001) 91 #define CORE_0_IEN_POWER_OFFSET (0x00000018ULL) 92 #define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \ 93 (APU_PCLI_CPU_STEP * (cpu_id)))) 94 #define APU_PCIL_CORE_X_IEN_POWER_MASK (0x00000001U) 95 #define CORE_0_IDS_POWER_OFFSET (0x0000001CULL) 96 #define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \ 97 (APU_PCLI_CPU_STEP * (cpu_id)))) 98 #define APU_PCIL_CORE_X_IDS_POWER_MASK (0x00000001U) 99 #define CORE_PWRDN_EN_BIT_MASK (0x1U) 100 101 /******************************************************************************* 102 * memory map related constants 103 ******************************************************************************/ 104 /* IPP 1.2/SPP 0.9 mapping */ 105 #define DEVICE0_BASE U(0xE8000000) /* psx, crl, iou */ 106 #define DEVICE0_SIZE U(0x08000000) 107 #define DEVICE1_BASE U(0xE2000000) /* gic */ 108 #define DEVICE1_SIZE U(0x00800000) 109 #define DEVICE2_BASE U(0xF1000000) /* uart, pmc_tap */ 110 #define DEVICE2_SIZE U(0x01000000) 111 #define CRF_BASE U(0xFD1A0000) 112 #define CRF_SIZE U(0x00600000) 113 #define IPI_BASE U(0xEB300000) 114 #define IPI_SIZE U(0x00100000) 115 116 /* CRL */ 117 #define VERSAL_NET_CRL U(0xEB5E0000) 118 #define VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET U(0x14C) 119 #define VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET U(0x348) 120 121 #define VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U) 122 123 /* IOU SCNTRS */ 124 #define IOU_SCNTRS_BASE U(0xEC920000) 125 #define IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0) 126 #define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) 127 128 #define IOU_SCNTRS_CONTROL_EN U(1) 129 130 #define APU_CLUSTER0 U(0xECC00000) 131 #define APU_RVBAR_L_0 U(0x40) 132 #define APU_RVBAR_H_0 U(0x44) 133 #define APU_CLUSTER_STEP U(0x100000) 134 135 #define SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL U(0xF1060504) 136 137 /******************************************************************************* 138 * IRQ constants 139 ******************************************************************************/ 140 #define VERSAL_NET_IRQ_SEC_PHY_TIMER U(29) 141 #define ARM_IRQ_SEC_PHY_TIMER 29 142 143 /******************************************************************************* 144 * UART related constants 145 ******************************************************************************/ 146 #define VERSAL_NET_UART0_BASE U(0xF1920000) 147 #define VERSAL_NET_UART1_BASE U(0xF1930000) 148 149 #define UART_BAUDRATE 115200 150 151 #if CONSOLE_IS(pl011) || CONSOLE_IS(dtb) 152 #define UART_BASE VERSAL_NET_UART0_BASE 153 # define UART_TYPE CONSOLE_PL011 154 #elif CONSOLE_IS(pl011_1) 155 #define UART_BASE VERSAL_NET_UART1_BASE 156 # define UART_TYPE CONSOLE_PL011 157 #elif CONSOLE_IS(dcc) 158 # define UART_BASE 0x0 159 # define UART_TYPE CONSOLE_DCC 160 #else 161 # error "invalid VERSAL_NET_CONSOLE" 162 #endif 163 164 /* Runtime console */ 165 #if defined(CONSOLE_RUNTIME) 166 #if RT_CONSOLE_IS(pl011) || RT_CONSOLE_IS(dtb) 167 # define RT_UART_BASE VERSAL_NET_UART0_BASE 168 # define RT_UART_TYPE CONSOLE_PL011 169 #elif RT_CONSOLE_IS(pl011_1) 170 # define RT_UART_BASE VERSAL_NET_UART1_BASE 171 # define RT_UART_TYPE CONSOLE_PL011 172 #elif RT_CONSOLE_IS(dcc) 173 # define RT_UART_BASE 0x0 174 # define RT_UART_TYPE CONSOLE_DCC 175 #else 176 # error "invalid CONSOLE_RUNTIME" 177 #endif 178 #endif 179 180 /* Processor core device IDs */ 181 #define PM_DEV_CLUSTER0_ACPU_0 (0x1810C0AFU) 182 #define PM_DEV_CLUSTER0_ACPU_1 (0x1810C0B0U) 183 #define PM_DEV_CLUSTER0_ACPU_2 (0x1810C0B1U) 184 #define PM_DEV_CLUSTER0_ACPU_3 (0x1810C0B2U) 185 186 #define PM_DEV_CLUSTER1_ACPU_0 (0x1810C0B3U) 187 #define PM_DEV_CLUSTER1_ACPU_1 (0x1810C0B4U) 188 #define PM_DEV_CLUSTER1_ACPU_2 (0x1810C0B5U) 189 #define PM_DEV_CLUSTER1_ACPU_3 (0x1810C0B6U) 190 191 #define PM_DEV_CLUSTER2_ACPU_0 (0x1810C0B7U) 192 #define PM_DEV_CLUSTER2_ACPU_1 (0x1810C0B8U) 193 #define PM_DEV_CLUSTER2_ACPU_2 (0x1810C0B9U) 194 #define PM_DEV_CLUSTER2_ACPU_3 (0x1810C0BAU) 195 196 #define PM_DEV_CLUSTER3_ACPU_0 (0x1810C0BBU) 197 #define PM_DEV_CLUSTER3_ACPU_1 (0x1810C0BCU) 198 #define PM_DEV_CLUSTER3_ACPU_2 (0x1810C0BDU) 199 #define PM_DEV_CLUSTER3_ACPU_3 (0x1810C0BEU) 200 201 #endif /* VERSAL_NET_DEF_H */ 202