1 /* 2 * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef VERSAL_NET_DEF_H 10 #define VERSAL_NET_DEF_H 11 12 #include <plat/arm/common/smccc_def.h> 13 #include <plat/common/common_def.h> 14 15 #define MAX_INTR_EL3 2 16 17 /* List all consoles */ 18 #define VERSAL_NET_CONSOLE_ID_pl011 U(1) 19 #define VERSAL_NET_CONSOLE_ID_pl011_0 U(1) 20 #define VERSAL_NET_CONSOLE_ID_pl011_1 U(2) 21 #define VERSAL_NET_CONSOLE_ID_dcc U(3) 22 23 #define CONSOLE_IS(con) (VERSAL_NET_CONSOLE_ID_ ## con == VERSAL_NET_CONSOLE) 24 25 /* Runtime console */ 26 #define RT_CONSOLE_ID_pl011 1 27 #define RT_CONSOLE_ID_pl011_0 1 28 #define RT_CONSOLE_ID_pl011_1 2 29 #define RT_CONSOLE_ID_dcc 3 30 #define RT_CONSOLE_ID_dtb 4 31 32 #define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME) 33 34 /* List all platforms */ 35 #define VERSAL_NET_SILICON U(0) 36 #define VERSAL_NET_SPP U(1) 37 #define VERSAL_NET_EMU U(2) 38 #define VERSAL_NET_QEMU U(3) 39 #define VERSAL_NET_QEMU_COSIM U(7) 40 41 /* For platform detection */ 42 #define PMC_TAP U(0xF11A0000) 43 #define PMC_TAP_VERSION (PMC_TAP + 0x4U) 44 # define PLATFORM_MASK GENMASK(27U, 24U) 45 # define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 46 47 /* Global timer reset */ 48 #define PSX_CRF U(0xEC200000) 49 #define ACPU0_CLK_CTRL U(0x10C) 50 #define ACPU_CLK_CTRL_CLKACT BIT(25) 51 52 #define RST_APU0_OFFSET U(0x300) 53 #define RST_APU_COLD_RESET BIT(0) 54 #define RST_APU_WARN_RESET BIT(4) 55 #define RST_APU_CLUSTER_COLD_RESET BIT(8) 56 #define RST_APU_CLUSTER_WARM_RESET BIT(9) 57 58 #define PSX_CRF_RST_TIMESTAMP_OFFSET U(0x33C) 59 60 #define APU_PCLI (0xECB10000ULL) 61 #define APU_PCLI_CPU_STEP (0x30ULL) 62 #define APU_PCLI_CLUSTER_CPU_STEP (4ULL * APU_PCLI_CPU_STEP) 63 #define APU_PCLI_CLUSTER_OFFSET U(0x8000) 64 #define APU_PCLI_CLUSTER_STEP U(0x1000) 65 #define PCLI_PREQ_OFFSET U(0x4) 66 #define PREQ_CHANGE_REQUEST BIT(0) 67 #define PCLI_PSTATE_OFFSET U(0x8) 68 #define PCLI_PSTATE_VAL_SET U(0x48) 69 #define PCLI_PSTATE_VAL_CLEAR U(0x38) 70 71 /* Firmware Image Package */ 72 #define VERSAL_NET_PRIMARY_CPU U(0) 73 74 #define CORE_0_ISR_WAKE_OFFSET (0x00000020ULL) 75 #define APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_WAKE_OFFSET + \ 76 (APU_PCLI_CPU_STEP * (cpu_id)))) 77 #define APU_PCIL_CORE_X_ISR_WAKE_MASK (0x00000001U) 78 #define CORE_0_IEN_WAKE_OFFSET (0x00000028ULL) 79 #define APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_WAKE_OFFSET + \ 80 (APU_PCLI_CPU_STEP * (cpu_id)))) 81 #define APU_PCIL_CORE_X_IEN_WAKE_MASK (0x00000001U) 82 #define CORE_0_IDS_WAKE_OFFSET (0x0000002CULL) 83 #define APU_PCIL_CORE_X_IDS_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_WAKE_OFFSET + \ 84 (APU_PCLI_CPU_STEP * (cpu_id)))) 85 #define APU_PCIL_CORE_X_IDS_WAKE_MASK (0x00000001U) 86 #define CORE_0_ISR_POWER_OFFSET (0x00000010ULL) 87 #define APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_POWER_OFFSET + \ 88 (APU_PCLI_CPU_STEP * (cpu_id)))) 89 #define APU_PCIL_CORE_X_ISR_POWER_MASK U(0x00000001) 90 #define CORE_0_IEN_POWER_OFFSET (0x00000018ULL) 91 #define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \ 92 (APU_PCLI_CPU_STEP * (cpu_id)))) 93 #define APU_PCIL_CORE_X_IEN_POWER_MASK (0x00000001U) 94 #define CORE_0_IDS_POWER_OFFSET (0x0000001CULL) 95 #define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \ 96 (APU_PCLI_CPU_STEP * (cpu_id)))) 97 #define APU_PCIL_CORE_X_IDS_POWER_MASK (0x00000001U) 98 #define CORE_PWRDN_EN_BIT_MASK (0x1U) 99 100 /******************************************************************************* 101 * memory map related constants 102 ******************************************************************************/ 103 /* IPP 1.2/SPP 0.9 mapping */ 104 #define DEVICE0_BASE U(0xE8000000) /* psx, crl, iou */ 105 #define DEVICE0_SIZE U(0x08000000) 106 #define DEVICE1_BASE U(0xE2000000) /* gic */ 107 #define DEVICE1_SIZE U(0x00800000) 108 #define DEVICE2_BASE U(0xF1000000) /* uart, pmc_tap */ 109 #define DEVICE2_SIZE U(0x01000000) 110 #define CRF_BASE U(0xFD1A0000) 111 #define CRF_SIZE U(0x00600000) 112 #define IPI_BASE U(0xEB300000) 113 #define IPI_SIZE U(0x00100000) 114 115 /* CRL */ 116 #define VERSAL_NET_CRL U(0xEB5E0000) 117 #define VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET U(0x14C) 118 #define VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET U(0x348) 119 120 #define VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U) 121 122 /* IOU SCNTRS */ 123 #define IOU_SCNTRS_BASE U(0xEC920000) 124 #define IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0) 125 #define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) 126 127 #define IOU_SCNTRS_CONTROL_EN U(1) 128 129 #define APU_CLUSTER0 U(0xECC00000) 130 #define APU_RVBAR_L_0 U(0x40) 131 #define APU_RVBAR_H_0 U(0x44) 132 #define APU_CLUSTER_STEP U(0x100000) 133 134 #define SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL U(0xF1060504) 135 136 /******************************************************************************* 137 * IRQ constants 138 ******************************************************************************/ 139 #define VERSAL_NET_IRQ_SEC_PHY_TIMER U(29) 140 #define ARM_IRQ_SEC_PHY_TIMER 29 141 142 /******************************************************************************* 143 * UART related constants 144 ******************************************************************************/ 145 #define VERSAL_NET_UART0_BASE U(0xF1920000) 146 #define VERSAL_NET_UART1_BASE U(0xF1930000) 147 148 #define UART_BAUDRATE 115200 149 150 #if CONSOLE_IS(pl011_1) 151 #define UART_BASE VERSAL_NET_UART1_BASE 152 #else 153 /* Default console is UART0 */ 154 #define UART_BASE VERSAL_NET_UART0_BASE 155 #endif 156 157 /* Runtime console */ 158 #if defined(CONSOLE_RUNTIME) 159 #if RT_CONSOLE_IS(pl011) || RT_CONSOLE_IS(dcc) || RT_CONSOLE_IS(dtb) 160 # define RT_UART_BASE VERSAL_NET_UART0_BASE 161 #elif RT_CONSOLE_IS(pl011_1) 162 # define RT_UART_BASE VERSAL_NET_UART1_BASE 163 #else 164 # error "invalid CONSOLE_RUNTIME" 165 #endif 166 #endif 167 168 /* Processor core device IDs */ 169 #define PM_DEV_CLUSTER0_ACPU_0 (0x1810C0AFU) 170 #define PM_DEV_CLUSTER0_ACPU_1 (0x1810C0B0U) 171 #define PM_DEV_CLUSTER0_ACPU_2 (0x1810C0B1U) 172 #define PM_DEV_CLUSTER0_ACPU_3 (0x1810C0B2U) 173 174 #define PM_DEV_CLUSTER1_ACPU_0 (0x1810C0B3U) 175 #define PM_DEV_CLUSTER1_ACPU_1 (0x1810C0B4U) 176 #define PM_DEV_CLUSTER1_ACPU_2 (0x1810C0B5U) 177 #define PM_DEV_CLUSTER1_ACPU_3 (0x1810C0B6U) 178 179 #define PM_DEV_CLUSTER2_ACPU_0 (0x1810C0B7U) 180 #define PM_DEV_CLUSTER2_ACPU_1 (0x1810C0B8U) 181 #define PM_DEV_CLUSTER2_ACPU_2 (0x1810C0B9U) 182 #define PM_DEV_CLUSTER2_ACPU_3 (0x1810C0BAU) 183 184 #define PM_DEV_CLUSTER3_ACPU_0 (0x1810C0BBU) 185 #define PM_DEV_CLUSTER3_ACPU_1 (0x1810C0BCU) 186 #define PM_DEV_CLUSTER3_ACPU_2 (0x1810C0BDU) 187 #define PM_DEV_CLUSTER3_ACPU_3 (0x1810C0BEU) 188 189 #endif /* VERSAL_NET_DEF_H */ 190