1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include <plat_common.h> 14 #include "versal_net_def.h" 15 16 /******************************************************************************* 17 * Generic platform constants 18 ******************************************************************************/ 19 20 /* Size of cacheable stacks */ 21 #define PLATFORM_STACK_SIZE U(0x440) 22 23 #define PLATFORM_CLUSTER_COUNT U(4) 24 #define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) /* 4 CPUs per cluster */ 25 26 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * PLATFORM_CORE_COUNT_PER_CLUSTER) 27 28 #define PLAT_MAX_PWR_LVL U(2) 29 #define PLAT_MAX_RET_STATE U(1) 30 #define PLAT_MAX_OFF_STATE U(2) 31 32 /******************************************************************************* 33 * BL31 specific defines. 34 ******************************************************************************/ 35 /* 36 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 37 * present). BL31_BASE is calculated using the current BL31 debug size plus a 38 * little space for growth. 39 */ 40 #ifndef VERSAL_NET_ATF_MEM_BASE 41 # define BL31_BASE U(0xBBF00000) 42 # define BL31_LIMIT U(0xBC000000) 43 #else 44 # define BL31_BASE U(VERSAL_NET_ATF_MEM_BASE) 45 # define BL31_LIMIT U(VERSAL_NET_ATF_MEM_BASE + VERSAL_NET_ATF_MEM_SIZE) 46 # ifdef VERSAL_NET_ATF_MEM_PROGBITS_SIZE 47 # define BL31_PROGBITS_LIMIT U(VERSAL_NET_ATF_MEM_BASE + \ 48 VERSAL_NET_ATF_MEM_PROGBITS_SIZE) 49 # endif 50 #endif 51 52 /******************************************************************************* 53 * BL32 specific defines. 54 ******************************************************************************/ 55 #ifndef VERSAL_NET_BL32_MEM_BASE 56 # define BL32_BASE U(0x60000000) 57 # define BL32_LIMIT U(0x80000000) 58 #else 59 # define BL32_BASE U(VERSAL_NET_BL32_MEM_BASE) 60 # define BL32_LIMIT U(VERSAL_NET_BL32_MEM_BASE + VERSAL_NET_BL32_MEM_SIZE) 61 #endif 62 63 /******************************************************************************* 64 * BL33 specific defines. 65 ******************************************************************************/ 66 #ifndef PRELOADED_BL33_BASE 67 # define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) 68 #else 69 # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) 70 #endif 71 72 /******************************************************************************* 73 * TSP specific defines. 74 ******************************************************************************/ 75 #define TSP_SEC_MEM_BASE BL32_BASE 76 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) 77 78 /* ID of the secure physical generic timer interrupt used by the TSP */ 79 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 80 81 /******************************************************************************* 82 * Platform specific page table and MMU setup constants 83 ******************************************************************************/ 84 #define PLAT_DDR_LOWMEM_MAX U(0x80000000) 85 86 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U) 87 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U) 88 89 #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) 90 91 #define PLAT_OCM_BASE U(0xBBF00000) 92 #define PLAT_OCM_LIMIT U(0xBC000000) 93 94 #define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) 95 96 #ifndef MAX_MMAP_REGIONS 97 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 98 #define MAX_MMAP_REGIONS 9 99 #else 100 #define MAX_MMAP_REGIONS 8 101 #endif 102 #endif 103 104 #ifndef MAX_XLAT_TABLES 105 #define MAX_XLAT_TABLES U(9) 106 #endif 107 108 #define CACHE_WRITEBACK_SHIFT U(6) 109 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 110 111 #define PLAT_ARM_GICD_BASE U(0xE2000000) 112 #define PLAT_ARM_GICR_BASE U(0xE2060000) 113 114 /* 115 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 116 * terminology. On a GICv2 system or mode, the lists will be merged and treated 117 * as Group 0 interrupts. 118 */ 119 #define PLAT_VERSAL_NET_IPI_IRQ 89 120 #define PLAT_VERSAL_IPI_IRQ PLAT_VERSAL_NET_IPI_IRQ 121 122 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 123 INTR_PROP_DESC(VERSAL_NET_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 124 GIC_INTR_CFG_LEVEL) 125 126 #define PLAT_ARM_G0_IRQ_PROPS(grp) \ 127 INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \ 128 GIC_INTR_CFG_EDGE), \ 129 INTR_PROP_DESC(CPU_PWR_DOWN_REQ_INTR, GIC_HIGHEST_SEC_PRIORITY, grp, \ 130 GIC_INTR_CFG_EDGE) 131 132 #define IRQ_MAX 200U 133 134 #endif /* PLATFORM_DEF_H */ 135