10bf622deSMichal Simek /* 20bf622deSMichal Simek * Copyright (c) 2022, Xilinx, Inc. All rights reserved. 3*bfd06265SMichal Simek * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 40bf622deSMichal Simek * 50bf622deSMichal Simek * SPDX-License-Identifier: BSD-3-Clause 60bf622deSMichal Simek */ 70bf622deSMichal Simek 80bf622deSMichal Simek /* Versal IPI management enums and defines */ 90bf622deSMichal Simek 100bf622deSMichal Simek #ifndef PLAT_IPI_H 110bf622deSMichal Simek #define PLAT_IPI_H 120bf622deSMichal Simek 130bf622deSMichal Simek #include <stdint.h> 140bf622deSMichal Simek 150bf622deSMichal Simek #include <ipi.h> 160bf622deSMichal Simek 170bf622deSMichal Simek /********************************************************************* 180bf622deSMichal Simek * IPI agent IDs macros 190bf622deSMichal Simek ********************************************************************/ 200bf622deSMichal Simek #define IPI_ID_PMC 1U 210bf622deSMichal Simek #define IPI_ID_APU 2U 220bf622deSMichal Simek #define IPI_ID_RPU0 3U 230bf622deSMichal Simek #define IPI_ID_RPU1 4U 240bf622deSMichal Simek #define IPI_ID_3 5U 250bf622deSMichal Simek #define IPI_ID_4 6U 260bf622deSMichal Simek #define IPI_ID_5 7U 270bf622deSMichal Simek #define IPI_ID_MAX 8U 280bf622deSMichal Simek 290bf622deSMichal Simek /********************************************************************* 300bf622deSMichal Simek * IPI message buffers 310bf622deSMichal Simek ********************************************************************/ 320bf622deSMichal Simek #define IPI_BUFFER_BASEADDR (0xEB3F0000U) 330bf622deSMichal Simek 34*bfd06265SMichal Simek #define IPI_BUFFER_LOCAL_BASE (IPI_BUFFER_BASEADDR + 0x400U) 35*bfd06265SMichal Simek #define IPI_BUFFER_REMOTE_BASE (IPI_BUFFER_BASEADDR + 0x200U) 360bf622deSMichal Simek 37*bfd06265SMichal Simek #define IPI_BUFFER_TARGET_LOCAL_OFFSET 0x80U 38*bfd06265SMichal Simek #define IPI_BUFFER_TARGET_REMOTE_OFFSET 0x40U 390bf622deSMichal Simek 400bf622deSMichal Simek #define IPI_BUFFER_MAX_WORDS 8 410bf622deSMichal Simek 420bf622deSMichal Simek #define IPI_BUFFER_REQ_OFFSET 0x0U 430bf622deSMichal Simek #define IPI_BUFFER_RESP_OFFSET 0x20U 440bf622deSMichal Simek 450bf622deSMichal Simek /********************************************************************* 460bf622deSMichal Simek * Platform specific IPI API declarations 470bf622deSMichal Simek ********************************************************************/ 480bf622deSMichal Simek 490bf622deSMichal Simek /* Configure IPI table for versal_net */ 500bf622deSMichal Simek void versal_net_ipi_config_table_init(void); 510bf622deSMichal Simek 52b2258ce3SMichal Simek /******************************************************************************* 53b2258ce3SMichal Simek * IPI registers and bitfields 54b2258ce3SMichal Simek ******************************************************************************/ 55b2258ce3SMichal Simek #define IPI0_REG_BASE (0xEB330000U) 56b2258ce3SMichal Simek #define IPI0_TRIG_BIT (1 << 2) 57b2258ce3SMichal Simek #define PMC_IPI_TRIG_BIT (1 << 1) 58b2258ce3SMichal Simek #define IPI1_REG_BASE (0xEB340000U) 59b2258ce3SMichal Simek #define IPI1_TRIG_BIT (1 << 3) 60b2258ce3SMichal Simek #define IPI2_REG_BASE (0xEB350000U) 61b2258ce3SMichal Simek #define IPI2_TRIG_BIT (1 << 4) 62b2258ce3SMichal Simek #define IPI3_REG_BASE (0xEB360000U) 63b2258ce3SMichal Simek #define IPI3_TRIG_BIT (1 << 5) 64b2258ce3SMichal Simek #define IPI4_REG_BASE (0xEB370000U) 65b2258ce3SMichal Simek #define IPI4_TRIG_BIT (1 << 6) 66b2258ce3SMichal Simek #define IPI5_REG_BASE (0xEB380000U) 67b2258ce3SMichal Simek #define IPI5_TRIG_BIT (1 << 7) 68b2258ce3SMichal Simek 690bf622deSMichal Simek #endif /* PLAT_IPI_H */ 70