1 /* 2 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/fdt_fixup.h> 16 #include <common/fdt_wrappers.h> 17 #include <drivers/arm/pl011.h> 18 #include <drivers/console.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 #include <libfdt.h> 22 #include <plat/common/platform.h> 23 #include <plat_arm.h> 24 25 #include <plat_private.h> 26 #include <plat_startup.h> 27 #include <versal_net_def.h> 28 29 static entry_point_info_t bl32_image_ep_info; 30 static entry_point_info_t bl33_image_ep_info; 31 static console_t versal_net_runtime_console; 32 33 /* 34 * Return a pointer to the 'entry_point_info' structure of the next image for 35 * the security state specified. BL33 corresponds to the non-secure image type 36 * while BL32 corresponds to the secure image type. A NULL pointer is returned 37 * if the image does not exist. 38 */ 39 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 40 { 41 assert(sec_state_is_valid(type)); 42 43 if (type == NON_SECURE) { 44 return &bl33_image_ep_info; 45 } 46 47 return &bl32_image_ep_info; 48 } 49 50 /* 51 * Set the build time defaults,if we can't find any config data. 52 */ 53 static inline void bl31_set_default_config(void) 54 { 55 bl32_image_ep_info.pc = BL32_BASE; 56 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 57 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 58 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 59 DISABLE_ALL_EXCEPTIONS); 60 } 61 62 /* 63 * Perform any BL31 specific platform actions. Here is an opportunity to copy 64 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 65 * are lost (potentially). This needs to be done before the MMU is initialized 66 * so that the memory layout can be used while creating page tables. 67 */ 68 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 69 u_register_t arg2, u_register_t arg3) 70 { 71 uint32_t uart_clock; 72 int32_t rc; 73 74 board_detection(); 75 76 switch (platform_id) { 77 case VERSAL_NET_SPP: 78 cpu_clock = 1000000; 79 uart_clock = 1000000; 80 break; 81 case VERSAL_NET_EMU: 82 cpu_clock = 3660000; 83 uart_clock = 25000000; 84 break; 85 case VERSAL_NET_QEMU: 86 /* Random values now */ 87 cpu_clock = 100000000; 88 uart_clock = 25000000; 89 break; 90 case VERSAL_NET_SILICON: 91 default: 92 panic(); 93 } 94 95 /* Initialize the console to provide early debug support */ 96 rc = console_pl011_register(VERSAL_NET_UART_BASE, uart_clock, 97 VERSAL_NET_UART_BAUDRATE, 98 &versal_net_runtime_console); 99 if (rc == 0) { 100 panic(); 101 } 102 103 console_set_scope(&versal_net_runtime_console, CONSOLE_FLAG_BOOT | 104 CONSOLE_FLAG_RUNTIME); 105 106 NOTICE("TF-A running on Xilinx %s %d.%d\n", board_name_decode(), 107 platform_version / 10U, platform_version % 10U); 108 109 /* Initialize the platform config for future decision making */ 110 versal_net_config_setup(); 111 /* There are no parameters from BL2 if BL31 is a reset vector */ 112 assert(arg0 == 0U); 113 assert(arg1 == 0U); 114 115 /* 116 * Do initial security configuration to allow DRAM/device access. On 117 * Base VERSAL_NET only DRAM security is programmable (via TrustZone), but 118 * other platforms might have more programmable security devices 119 * present. 120 */ 121 122 /* Populate common information for BL32 and BL33 */ 123 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 124 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 125 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 126 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 127 128 bl31_set_default_config(); 129 130 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 131 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 132 } 133 134 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 135 136 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 137 { 138 static uint32_t index; 139 uint32_t i; 140 141 /* Validate 'handler' and 'id' parameters */ 142 if (handler == NULL || index >= MAX_INTR_EL3) { 143 return -EINVAL; 144 } 145 146 /* Check if a handler has already been registered */ 147 for (i = 0; i < index; i++) { 148 if (id == type_el3_interrupt_table[i].id) { 149 return -EALREADY; 150 } 151 } 152 153 type_el3_interrupt_table[index].id = id; 154 type_el3_interrupt_table[index].handler = handler; 155 156 index++; 157 158 return 0; 159 } 160 161 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 162 void *handle, void *cookie) 163 { 164 uint32_t intr_id; 165 uint32_t i; 166 interrupt_type_handler_t handler = NULL; 167 168 intr_id = plat_ic_get_pending_interrupt_id(); 169 170 for (i = 0; i < MAX_INTR_EL3; i++) { 171 if (intr_id == type_el3_interrupt_table[i].id) { 172 handler = type_el3_interrupt_table[i].handler; 173 } 174 } 175 176 if (handler != NULL) { 177 handler(intr_id, flags, handle, cookie); 178 } 179 180 return 0; 181 } 182 183 void bl31_platform_setup(void) 184 { 185 /* Initialize the gic cpu and distributor interfaces */ 186 plat_versal_net_gic_driver_init(); 187 plat_versal_net_gic_init(); 188 } 189 190 void bl31_plat_runtime_setup(void) 191 { 192 uint64_t flags = 0; 193 int32_t rc; 194 195 set_interrupt_rm_flag(flags, NON_SECURE); 196 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 197 rdo_el3_interrupt_handler, flags); 198 if (rc != 0) { 199 panic(); 200 } 201 } 202 203 /* 204 * Perform the very early platform specific architectural setup here. 205 */ 206 void bl31_plat_arch_setup(void) 207 { 208 const mmap_region_t bl_regions[] = { 209 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 210 MT_MEMORY | MT_RW | MT_SECURE), 211 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 212 MT_CODE | MT_SECURE), 213 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 214 MT_RO_DATA | MT_SECURE), 215 {0} 216 }; 217 218 setup_page_tables(bl_regions, plat_versal_net_get_mmap()); 219 enable_mmu(0); 220 } 221