1 /* 2 * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 #include <plat/common/platform.h> 18 #include <plat_arm.h> 19 #include <plat_console.h> 20 #include <plat_clkfunc.h> 21 22 #include <plat_fdt.h> 23 #include <plat_private.h> 24 #include <plat_startup.h> 25 #include <pm_api_sys.h> 26 #include <pm_client.h> 27 #include <pm_ipi.h> 28 #include <versal_net_def.h> 29 30 static entry_point_info_t bl32_image_ep_info; 31 static entry_point_info_t bl33_image_ep_info; 32 33 static const uintptr_t gicr_base_addrs[2] = { 34 PLAT_ARM_GICR_BASE, /* GICR Base address of the primary CPU */ 35 0U /* Zero Termination */ 36 }; 37 38 /* 39 * Return a pointer to the 'entry_point_info' structure of the next image for 40 * the security state specified. BL33 corresponds to the non-secure image type 41 * while BL32 corresponds to the secure image type. A NULL pointer is returned 42 * if the image does not exist. 43 */ 44 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 45 { 46 assert(sec_state_is_valid(type)); 47 48 if (type == NON_SECURE) { 49 return &bl33_image_ep_info; 50 } 51 52 return &bl32_image_ep_info; 53 } 54 55 /* 56 * Set the build time defaults,if we can't find any config data. 57 */ 58 static inline void bl31_set_default_config(void) 59 { 60 bl32_image_ep_info.pc = BL32_BASE; 61 bl32_image_ep_info.spsr = arm_get_spsr(BL32_IMAGE_ID); 62 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 63 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 64 DISABLE_ALL_EXCEPTIONS); 65 } 66 67 /* Define read and write function for clusterbusqos register */ 68 DEFINE_RENAME_SYSREG_RW_FUNCS(cluster_bus_qos, S3_0_C15_C4_4) 69 70 static void versal_net_setup_qos(void) 71 { 72 int ret; 73 74 ret = read_cluster_bus_qos(); 75 INFO("BL31: default cluster bus qos: 0x%x\n", ret); 76 write_cluster_bus_qos(0); 77 ret = read_cluster_bus_qos(); 78 INFO("BL31: cluster bus qos written: 0x%x\n", ret); 79 } 80 81 /* 82 * Perform any BL31 specific platform actions. Here is an opportunity to copy 83 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 84 * are lost (potentially). This needs to be done before the MMU is initialized 85 * so that the memory layout can be used while creating page tables. 86 */ 87 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 88 u_register_t arg2, u_register_t arg3) 89 { 90 (void)arg0; 91 (void)arg1; 92 (void)arg2; 93 (void)arg3; 94 95 #if !(TFA_NO_PM) 96 uint64_t tfa_handoff_addr, buff[HANDOFF_PARAMS_MAX_SIZE] = {0}; 97 uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE; 98 enum pm_ret_status ret_status; 99 #endif /* !(TFA_NO_PM) */ 100 101 board_detection(); 102 103 switch (platform_id) { 104 case VERSAL_NET_SPP: 105 cpu_clock = 1000000; 106 break; 107 case VERSAL_NET_EMU: 108 cpu_clock = 3660000; 109 break; 110 case VERSAL_NET_QEMU: 111 /* Random values now */ 112 cpu_clock = 100000000; 113 break; 114 case VERSAL_NET_SILICON: 115 cpu_clock = 100000000; 116 break; 117 default: 118 panic(); 119 } 120 121 syscnt_freq_config_setup(); 122 123 set_cnt_freq(); 124 125 /* Initialize the platform config for future decision making */ 126 versal_net_config_setup(); 127 128 setup_console(); 129 130 NOTICE("TF-A running on %s %d.%d\n", board_name_decode(), 131 platform_version / 10U, platform_version % 10U); 132 133 versal_net_setup_qos(); 134 135 136 /* 137 * Do initial security configuration to allow DRAM/device access. On 138 * Base VERSAL_NET only DRAM security is programmable (via TrustZone), but 139 * other platforms might have more programmable security devices 140 * present. 141 */ 142 143 /* Populate common information for BL32 and BL33 */ 144 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 145 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 146 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 147 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 148 #if !(TFA_NO_PM) 149 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1U, PM_LOAD_GET_HANDOFF_PARAMS, 150 (uintptr_t)buff >> 32U, (uintptr_t)buff, max_size); 151 152 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); 153 if (ret_status == PM_RET_SUCCESS) { 154 enum xbl_handoff xbl_ret; 155 156 tfa_handoff_addr = (uintptr_t)&buff; 157 158 xbl_ret = xbl_handover(&bl32_image_ep_info, &bl33_image_ep_info, 159 tfa_handoff_addr); 160 if (xbl_ret != XBL_HANDOFF_SUCCESS) { 161 ERROR("BL31: PLM to TF-A handover failed %u\n", xbl_ret); 162 panic(); 163 } 164 165 INFO("BL31: PLM to TF-A handover success\n"); 166 167 } else { 168 INFO("BL31: setting up default configs\n"); 169 170 bl31_set_default_config(); 171 } 172 #else 173 bl31_set_default_config(); 174 #endif /* !(TFA_NO_PM) */ 175 176 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 177 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 178 } 179 180 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 181 182 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 183 { 184 static uint32_t index; 185 uint32_t i; 186 int32_t ret = 0; 187 188 /* Validate 'handler' and 'id' parameters */ 189 if ((handler == NULL) || (index >= MAX_INTR_EL3)) { 190 ret = -EINVAL; 191 goto exit_label; 192 } 193 194 /* Check if a handler has already been registered */ 195 for (i = 0; i < index; i++) { 196 if (id == type_el3_interrupt_table[i].id) { 197 ret = -EALREADY; 198 goto exit_label; 199 } 200 } 201 202 type_el3_interrupt_table[index].id = id; 203 type_el3_interrupt_table[index].handler = handler; 204 205 index++; 206 207 exit_label: 208 return ret; 209 } 210 211 #if SDEI_SUPPORT 212 static int rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 213 void *handle, void *cookie) 214 #else 215 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 216 void *handle, void *cookie) 217 #endif 218 { 219 uint32_t intr_id; 220 uint32_t i; 221 interrupt_type_handler_t handler = NULL; 222 223 #if SDEI_SUPPORT 224 /* when SDEI_SUPPORT is enabled, ehf_el3_interrupt_handler 225 * reads the interrupt id prior to calling the 226 * rdo_el3_interrupt_handler and passes that id to the 227 * handler. 228 */ 229 intr_id = id; 230 #else 231 intr_id = plat_ic_get_pending_interrupt_id(); 232 #endif 233 234 for (i = 0; i < MAX_INTR_EL3; i++) { 235 if (intr_id == type_el3_interrupt_table[i].id) { 236 handler = type_el3_interrupt_table[i].handler; 237 } 238 } 239 240 if (handler != NULL) { 241 (void)handler(intr_id, flags, handle, cookie); 242 } 243 244 return 0; 245 } 246 247 void bl31_platform_setup(void) 248 { 249 prepare_dtb(); 250 251 gic_set_gicr_frames(gicr_base_addrs); 252 } 253 254 void bl31_plat_runtime_setup(void) 255 { 256 #if !SDEI_SUPPORT 257 uint64_t flags = 0; 258 int32_t rc; 259 260 set_interrupt_rm_flag(flags, NON_SECURE); 261 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 262 rdo_el3_interrupt_handler, flags); 263 if (rc != 0) { 264 panic(); 265 } 266 #else 267 ehf_register_priority_handler(PLAT_IPI_PRI, rdo_el3_interrupt_handler); 268 #endif 269 } 270 271 /* 272 * Perform the very early platform specific architectural setup here. 273 */ 274 void bl31_plat_arch_setup(void) 275 { 276 const mmap_region_t bl_regions[] = { 277 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 278 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 279 MT_MEMORY | MT_RW | MT_NS), 280 #endif 281 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 282 MT_MEMORY | MT_RW | MT_SECURE), 283 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 284 MT_CODE | MT_SECURE), 285 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 286 MT_RO_DATA | MT_SECURE), 287 {0} 288 }; 289 290 setup_page_tables(bl_regions, plat_get_mmap()); 291 enable_mmu(0); 292 } 293