1/* 2 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9#include <asm_macros.S> 10 11#include <arch.h> 12#include <drivers/arm/gicv3.h> 13 14#include <platform_def.h> 15 16 .globl plat_secondary_cold_boot_setup 17 .globl plat_is_my_cpu_primary 18 .globl platform_mem_init 19 .globl plat_my_core_pos 20 .globl plat_crash_console_init 21 .globl plat_crash_console_putc 22 .globl plat_crash_console_flush 23 24 /* ----------------------------------------------------- 25 * void plat_secondary_cold_boot_setup (void); 26 * 27 * This function performs any platform specific actions 28 * needed for a secondary cpu after a cold reset e.g 29 * mark the cpu's presence, mechanism to place it in a 30 * holding pen etc. 31 * TODO: Should we read the PSYS register to make sure 32 * that the request has gone through. 33 * ----------------------------------------------------- 34 */ 35func plat_secondary_cold_boot_setup 36 mrs x0, mpidr_el1 37 38 /* 39 * There is no sane reason to come out of this wfi. This 40 * cpu will be powered on and reset by the cpu_on pm api 41 */ 42 dsb sy 43 bl plat_panic_handler 44endfunc plat_secondary_cold_boot_setup 45 46func plat_is_my_cpu_primary 47 mov x9, x30 48 bl plat_my_core_pos 49 cmp x0, #VERSAL_NET_PRIMARY_CPU 50 cset x0, eq 51 ret x9 52endfunc plat_is_my_cpu_primary 53 54 /* ----------------------------------------------------- 55 * unsigned int plat_my_core_pos(void) 56 * This function uses the plat_core_pos_by_mpidr() 57 * definition to get the index of the calling CPU. 58 * ----------------------------------------------------- 59 */ 60func plat_my_core_pos 61 mrs x0, mpidr_el1 62 b plat_core_pos_by_mpidr 63endfunc plat_my_core_pos 64 65 /* --------------------------------------------------------------------- 66 * We don't need to carry out any memory initialization on Versal NET 67 * platform. The Secure RAM is accessible straight away. 68 * --------------------------------------------------------------------- 69 */ 70func platform_mem_init 71 ret 72endfunc platform_mem_init 73 74 75 /* --------------------------------------------- 76 * int plat_crash_console_init(void) 77 * Function to initialize the crash console 78 * without a C Runtime to print crash report. 79 * Clobber list : x0, x1, x2 80 * --------------------------------------------- 81 */ 82func plat_crash_console_init 83/* mov_imm x0, PLAT_VERSAL_NET_CRASH_UART_BASE 84 mov_imm x1, PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ 85 mov_imm x2, VERSAL_NET_CONSOLE_BAUDRATE 86 b console_pl011_core_init */ 87endfunc plat_crash_console_init 88 89 /* --------------------------------------------- 90 * int plat_crash_console_putc(int c) 91 * Function to print a character on the crash 92 * console without a C Runtime. 93 * Clobber list : x1, x2 94 * --------------------------------------------- 95 */ 96func plat_crash_console_putc 97 mov_imm x1, PLAT_VERSAL_NET_CRASH_UART_BASE 98 b console_pl011_core_putc 99endfunc plat_crash_console_putc 100 101 /* --------------------------------------------- 102 * void plat_crash_console_flush() 103 * Function to force a write of all buffered 104 * data that hasn't been output. 105 * Out : void. 106 * Clobber list : x0, x1 107 * --------------------------------------------- 108 */ 109func plat_crash_console_flush 110 mov_imm x0, PLAT_VERSAL_NET_CRASH_UART_BASE 111 b console_pl011_core_flush 112endfunc plat_crash_console_flush 113