1 /* 2 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 3 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* 9 * Versal IPI agent registers access management 10 */ 11 12 #include <lib/utils_def.h> 13 #include <ipi.h> 14 #include <plat_ipi.h> 15 16 /* versal ipi configuration table */ 17 static const struct ipi_config versal_ipi_table[] = { 18 /* PMC IPI */ 19 [IPI_ID_PMC] = { 20 .ipi_bit_mask = PMC_IPI_TRIG_BIT, 21 .ipi_reg_base = PMC_REG_BASE, 22 .secure_only = 0U, 23 }, 24 25 /* A72 IPI */ 26 [IPI_ID_APU] = { 27 .ipi_bit_mask = IPI0_TRIG_BIT, 28 .ipi_reg_base = IPI0_REG_BASE, 29 .secure_only = 0U, 30 }, 31 32 /* RPU0 IPI */ 33 [IPI_ID_RPU0] = { 34 .ipi_bit_mask = IPI1_TRIG_BIT, 35 .ipi_reg_base = IPI1_REG_BASE, 36 .secure_only = 0U, 37 }, 38 39 /* RPU1 IPI */ 40 [IPI_ID_RPU1] = { 41 .ipi_bit_mask = IPI2_TRIG_BIT, 42 .ipi_reg_base = IPI2_REG_BASE, 43 .secure_only = 0U, 44 }, 45 46 /* IPI3 IPI */ 47 [IPI_ID_3] = { 48 .ipi_bit_mask = IPI3_TRIG_BIT, 49 .ipi_reg_base = IPI3_REG_BASE, 50 .secure_only = 0U, 51 }, 52 53 /* IPI4 IPI */ 54 [IPI_ID_4] = { 55 .ipi_bit_mask = IPI4_TRIG_BIT, 56 .ipi_reg_base = IPI4_REG_BASE, 57 .secure_only = 0U, 58 }, 59 60 /* IPI5 IPI */ 61 [IPI_ID_5] = { 62 .ipi_bit_mask = IPI5_TRIG_BIT, 63 .ipi_reg_base = IPI5_REG_BASE, 64 .secure_only = 0U, 65 }, 66 }; 67 68 /* versal_ipi_config_table_init() - Initialize versal IPI configuration data 69 * 70 * @ipi_config_table - IPI configuration table 71 * @ipi_total - Total number of IPI available 72 * 73 */ 74 void versal_ipi_config_table_init(void) 75 { 76 ipi_config_table_init(versal_ipi_table, ARRAY_SIZE(versal_ipi_table)); 77 } 78