1 /* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <plat_private.h> 8 #include <platform_def.h> 9 10 #include <common/interrupt_props.h> 11 #include <drivers/arm/gicv3.h> 12 #include <lib/utils.h> 13 #include <plat/common/platform.h> 14 15 /****************************************************************************** 16 * The following functions are defined as weak to allow a platform to override 17 * the way the GICv3 driver is initialised and used. 18 *****************************************************************************/ 19 #pragma weak plat_versal_gic_driver_init 20 #pragma weak plat_versal_gic_init 21 #pragma weak plat_versal_gic_cpuif_enable 22 #pragma weak plat_versal_gic_cpuif_disable 23 #pragma weak plat_versal_gic_pcpu_init 24 #pragma weak plat_versal_gic_redistif_on 25 #pragma weak plat_versal_gic_redistif_off 26 27 /* The GICv3 driver only needs to be initialized in EL3 */ 28 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 29 30 static const interrupt_prop_t versal_interrupt_props[] = { 31 PLAT_VERSAL_G1S_IRQ_PROPS(INTR_GROUP1S), 32 PLAT_VERSAL_G0_IRQ_PROPS(INTR_GROUP0) 33 }; 34 35 /* 36 * We save and restore the GICv3 context on system suspend. Allocate the 37 * data in the designated EL3 Secure carve-out memory. 38 */ 39 static gicv3_redist_ctx_t rdist_ctx __section(".versal_el3_tzc_dram"); 40 static gicv3_dist_ctx_t dist_ctx __section(".versal_el3_tzc_dram"); 41 42 /* 43 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register 44 * to core position. 45 * 46 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity 47 * values read from GICR_TYPER don't have an MT field. To reuse the same 48 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into 49 * that read from GICR_TYPER. 50 * 51 * Assumptions: 52 * 53 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set; 54 * - No CPUs implemented in the system use affinity level 3. 55 */ 56 static uint32_t versal_gicv3_mpidr_hash(u_register_t mpidr) 57 { 58 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); 59 return versal_calc_core_pos(mpidr); 60 } 61 62 static const gicv3_driver_data_t versal_gic_data __unused = { 63 .gicd_base = PLAT_VERSAL_GICD_BASE, 64 .gicr_base = PLAT_VERSAL_GICR_BASE, 65 .interrupt_props = versal_interrupt_props, 66 .interrupt_props_num = ARRAY_SIZE(versal_interrupt_props), 67 .rdistif_num = PLATFORM_CORE_COUNT, 68 .rdistif_base_addrs = rdistif_base_addrs, 69 .mpidr_to_core_pos = versal_gicv3_mpidr_hash 70 }; 71 72 void __init plat_versal_gic_driver_init(void) 73 { 74 /* 75 * The GICv3 driver is initialized in EL3 and does not need 76 * to be initialized again in SEL1. This is because the S-EL1 77 * can use GIC system registers to manage interrupts and does 78 * not need GIC interface base addresses to be configured. 79 */ 80 #if IMAGE_BL31 81 gicv3_driver_init(&versal_gic_data); 82 #endif 83 } 84 85 /****************************************************************************** 86 * Versal common helper to initialize the GIC. Only invoked by BL31 87 *****************************************************************************/ 88 void __init plat_versal_gic_init(void) 89 { 90 gicv3_distif_init(); 91 gicv3_rdistif_init(plat_my_core_pos()); 92 gicv3_cpuif_enable(plat_my_core_pos()); 93 } 94 95 /****************************************************************************** 96 * Versal common helper to enable the GIC CPU interface 97 *****************************************************************************/ 98 void plat_versal_gic_cpuif_enable(void) 99 { 100 gicv3_cpuif_enable(plat_my_core_pos()); 101 } 102 103 /****************************************************************************** 104 * Versal common helper to disable the GIC CPU interface 105 *****************************************************************************/ 106 void plat_versal_gic_cpuif_disable(void) 107 { 108 gicv3_cpuif_disable(plat_my_core_pos()); 109 } 110 111 /****************************************************************************** 112 * Versal common helper to initialize the per-cpu redistributor interface in 113 * GICv3 114 *****************************************************************************/ 115 void plat_versal_gic_pcpu_init(void) 116 { 117 gicv3_rdistif_init(plat_my_core_pos()); 118 } 119 120 /****************************************************************************** 121 * Versal common helpers to power GIC redistributor interface 122 *****************************************************************************/ 123 void plat_versal_gic_redistif_on(void) 124 { 125 gicv3_rdistif_on(plat_my_core_pos()); 126 } 127 128 void plat_versal_gic_redistif_off(void) 129 { 130 gicv3_rdistif_off(plat_my_core_pos()); 131 } 132 133 /****************************************************************************** 134 * Versal common helper to save & restore the GICv3 on resume from system 135 * suspend 136 *****************************************************************************/ 137 void plat_versal_gic_save(void) 138 { 139 /* 140 * If an ITS is available, save its context before 141 * the Redistributor using: 142 * gicv3_its_save_disable(gits_base, &its_ctx[i]) 143 * Additionnaly, an implementation-defined sequence may 144 * be required to save the whole ITS state. 145 */ 146 147 /* 148 * Save the GIC Redistributors and ITS contexts before the 149 * Distributor context. As we only handle SYSTEM SUSPEND API, 150 * we only need to save the context of the CPU that is issuing 151 * the SYSTEM SUSPEND call, i.e. the current CPU. 152 */ 153 gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx); 154 155 /* Save the GIC Distributor context */ 156 gicv3_distif_save(&dist_ctx); 157 158 /* 159 * From here, all the components of the GIC can be safely powered down 160 * as long as there is an alternate way to handle wakeup interrupt 161 * sources. 162 */ 163 } 164 165 void plat_versal_gic_resume(void) 166 { 167 /* Restore the GIC Distributor context */ 168 gicv3_distif_init_restore(&dist_ctx); 169 170 /* 171 * Restore the GIC Redistributor and ITS contexts after the 172 * Distributor context. As we only handle SYSTEM SUSPEND API, 173 * we only need to restore the context of the CPU that issued 174 * the SYSTEM SUSPEND call. 175 */ 176 gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx); 177 178 /* 179 * If an ITS is available, restore its context after 180 * the Redistributor using: 181 * gicv3_its_restore(gits_base, &its_ctx[i]) 182 * An implementation-defined sequence may be required to 183 * restore the whole ITS state. The ITS must also be 184 * re-enabled after this sequence has been executed. 185 */ 186 } 187