1 /* 2 * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <plat_private.h> 9 #include <platform_def.h> 10 11 #include <common/interrupt_props.h> 12 #include <drivers/arm/gicv3.h> 13 #include <lib/utils.h> 14 #include <plat/common/platform.h> 15 16 /****************************************************************************** 17 * The following functions are defined as weak to allow a platform to override 18 * the way the GICv3 driver is initialised and used. 19 *****************************************************************************/ 20 #pragma weak plat_versal_gic_driver_init 21 #pragma weak plat_versal_gic_init 22 #pragma weak plat_versal_gic_cpuif_enable 23 #pragma weak plat_versal_gic_cpuif_disable 24 #pragma weak plat_versal_gic_pcpu_init 25 #pragma weak plat_versal_gic_redistif_on 26 #pragma weak plat_versal_gic_redistif_off 27 28 /* The GICv3 driver only needs to be initialized in EL3 */ 29 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 30 31 static const interrupt_prop_t versal_interrupt_props[] = { 32 PLAT_VERSAL_G1S_IRQ_PROPS(INTR_GROUP1S), 33 PLAT_VERSAL_G0_IRQ_PROPS(INTR_GROUP0) 34 }; 35 36 /* 37 * We save and restore the GICv3 context on system suspend. Allocate the 38 * data in the designated EL3 Secure carve-out memory. 39 */ 40 static gicv3_redist_ctx_t rdist_ctx __section(".versal_el3_tzc_dram"); 41 static gicv3_dist_ctx_t dist_ctx __section(".versal_el3_tzc_dram"); 42 43 /* 44 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register 45 * to core position. 46 * 47 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity 48 * values read from GICR_TYPER don't have an MT field. To reuse the same 49 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into 50 * that read from GICR_TYPER. 51 * 52 * Assumptions: 53 * 54 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set; 55 * - No CPUs implemented in the system use affinity level 3. 56 */ 57 static uint32_t versal_gicv3_mpidr_hash(u_register_t mpidr) 58 { 59 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); 60 return versal_calc_core_pos(mpidr); 61 } 62 63 static const gicv3_driver_data_t versal_gic_data __unused = { 64 .gicd_base = PLAT_GICD_BASE_VALUE, 65 .gicr_base = PLAT_GICR_BASE_VALUE, 66 .interrupt_props = versal_interrupt_props, 67 .interrupt_props_num = ARRAY_SIZE(versal_interrupt_props), 68 .rdistif_num = PLATFORM_CORE_COUNT, 69 .rdistif_base_addrs = rdistif_base_addrs, 70 .mpidr_to_core_pos = versal_gicv3_mpidr_hash 71 }; 72 73 void __init plat_versal_gic_driver_init(void) 74 { 75 /* 76 * The GICv3 driver is initialized in EL3 and does not need 77 * to be initialized again in SEL1. This is because the S-EL1 78 * can use GIC system registers to manage interrupts and does 79 * not need GIC interface base addresses to be configured. 80 */ 81 #if IMAGE_BL31 82 gicv3_driver_init(&versal_gic_data); 83 #endif 84 } 85 86 /****************************************************************************** 87 * Versal common helper to initialize the GIC. Only invoked by BL31 88 *****************************************************************************/ 89 void __init plat_versal_gic_init(void) 90 { 91 gicv3_distif_init(); 92 gicv3_rdistif_init(plat_my_core_pos()); 93 gicv3_cpuif_enable(plat_my_core_pos()); 94 } 95 96 /****************************************************************************** 97 * Versal common helper to enable the GIC CPU interface 98 *****************************************************************************/ 99 void plat_versal_gic_cpuif_enable(void) 100 { 101 gicv3_cpuif_enable(plat_my_core_pos()); 102 } 103 104 /****************************************************************************** 105 * Versal common helper to disable the GIC CPU interface 106 *****************************************************************************/ 107 void plat_versal_gic_cpuif_disable(void) 108 { 109 gicv3_cpuif_disable(plat_my_core_pos()); 110 } 111 112 /****************************************************************************** 113 * Versal common helper to initialize the per-cpu redistributor interface in 114 * GICv3 115 *****************************************************************************/ 116 void plat_versal_gic_pcpu_init(void) 117 { 118 gicv3_rdistif_init(plat_my_core_pos()); 119 } 120 121 /****************************************************************************** 122 * Versal common helpers to power GIC redistributor interface 123 *****************************************************************************/ 124 void plat_versal_gic_redistif_on(void) 125 { 126 gicv3_rdistif_on(plat_my_core_pos()); 127 } 128 129 void plat_versal_gic_redistif_off(void) 130 { 131 gicv3_rdistif_off(plat_my_core_pos()); 132 } 133 134 /****************************************************************************** 135 * Versal common helper to save & restore the GICv3 on resume from system 136 * suspend 137 *****************************************************************************/ 138 void plat_versal_gic_save(void) 139 { 140 /* 141 * If an ITS is available, save its context before 142 * the Redistributor using: 143 * gicv3_its_save_disable(gits_base, &its_ctx[i]) 144 * Additionnaly, an implementation-defined sequence may 145 * be required to save the whole ITS state. 146 */ 147 148 /* 149 * Save the GIC Redistributors and ITS contexts before the 150 * Distributor context. As we only handle SYSTEM SUSPEND API, 151 * we only need to save the context of the CPU that is issuing 152 * the SYSTEM SUSPEND call, i.e. the current CPU. 153 */ 154 gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx); 155 156 /* Save the GIC Distributor context */ 157 gicv3_distif_save(&dist_ctx); 158 159 /* 160 * From here, all the components of the GIC can be safely powered down 161 * as long as there is an alternate way to handle wakeup interrupt 162 * sources. 163 */ 164 } 165 166 void plat_versal_gic_resume(void) 167 { 168 /* Restore the GIC Distributor context */ 169 gicv3_distif_init_restore(&dist_ctx); 170 171 /* 172 * Restore the GIC Redistributor and ITS contexts after the 173 * Distributor context. As we only handle SYSTEM SUSPEND API, 174 * we only need to restore the context of the CPU that issued 175 * the SYSTEM SUSPEND call. 176 */ 177 gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx); 178 179 /* 180 * If an ITS is available, restore its context after 181 * the Redistributor using: 182 * gicv3_its_restore(gits_base, &its_ctx[i]) 183 * An implementation-defined sequence may be required to 184 * restore the whole ITS state. The ITS must also be 185 * re-enabled after this sequence has been executed. 186 */ 187 } 188