1 /* 2 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * APU specific definition of processors in the subsystem as well as functions 9 * for getting information about and changing state of the APU. 10 */ 11 12 #include <assert.h> 13 #include <plat_ipi.h> 14 #include <platform_def.h> 15 #include <versal_def.h> 16 #include <lib/bakery_lock.h> 17 #include <lib/mmio.h> 18 #include <lib/utils.h> 19 #include <drivers/arm/gicv3.h> 20 #include <drivers/arm/gic_common.h> 21 #include <plat/common/platform.h> 22 #include "pm_api_sys.h" 23 #include "pm_client.h" 24 #include "pm_defs.h" 25 26 #define UNDEFINED_CPUID (~0) 27 #define IRQ_MAX 142U 28 #define NUM_GICD_ISENABLER ((IRQ_MAX >> 5U) + 1U) 29 30 DEFINE_BAKERY_LOCK(pm_client_secure_lock); 31 32 static const struct pm_ipi apu_ipi = { 33 .local_ipi_id = IPI_ID_APU, 34 .remote_ipi_id = IPI_ID_PMC, 35 .buffer_base = IPI_BUFFER_APU_BASE, 36 }; 37 38 /* Order in pm_procs_all array must match cpu ids */ 39 static const struct pm_proc pm_procs_all[] = { 40 { 41 .node_id = XPM_DEVID_ACPU_0, 42 .ipi = &apu_ipi, 43 .pwrdn_mask = APU_0_PWRCTL_CPUPWRDWNREQ_MASK, 44 }, 45 { 46 .node_id = XPM_DEVID_ACPU_1, 47 .ipi = &apu_ipi, 48 .pwrdn_mask = APU_1_PWRCTL_CPUPWRDWNREQ_MASK, 49 } 50 }; 51 52 const struct pm_proc *primary_proc = &pm_procs_all[0]; 53 54 /* Interrupt to PM node index map */ 55 static enum pm_device_node_idx irq_node_map[IRQ_MAX + 1] = { 56 [13] = XPM_NODEIDX_DEV_GPIO, 57 [14] = XPM_NODEIDX_DEV_I2C_0, 58 [15] = XPM_NODEIDX_DEV_I2C_1, 59 [16] = XPM_NODEIDX_DEV_SPI_0, 60 [17] = XPM_NODEIDX_DEV_SPI_1, 61 [18] = XPM_NODEIDX_DEV_UART_0, 62 [19] = XPM_NODEIDX_DEV_UART_1, 63 [20] = XPM_NODEIDX_DEV_CAN_FD_0, 64 [21] = XPM_NODEIDX_DEV_CAN_FD_1, 65 [22] = XPM_NODEIDX_DEV_USB_0, 66 [23] = XPM_NODEIDX_DEV_USB_0, 67 [24] = XPM_NODEIDX_DEV_USB_0, 68 [25] = XPM_NODEIDX_DEV_USB_0, 69 [26] = XPM_NODEIDX_DEV_USB_0, 70 [37] = XPM_NODEIDX_DEV_TTC_0, 71 [38] = XPM_NODEIDX_DEV_TTC_0, 72 [39] = XPM_NODEIDX_DEV_TTC_0, 73 [40] = XPM_NODEIDX_DEV_TTC_1, 74 [41] = XPM_NODEIDX_DEV_TTC_1, 75 [42] = XPM_NODEIDX_DEV_TTC_1, 76 [43] = XPM_NODEIDX_DEV_TTC_2, 77 [44] = XPM_NODEIDX_DEV_TTC_2, 78 [45] = XPM_NODEIDX_DEV_TTC_2, 79 [46] = XPM_NODEIDX_DEV_TTC_3, 80 [47] = XPM_NODEIDX_DEV_TTC_3, 81 [48] = XPM_NODEIDX_DEV_TTC_3, 82 [56] = XPM_NODEIDX_DEV_GEM_0, 83 [57] = XPM_NODEIDX_DEV_GEM_0, 84 [58] = XPM_NODEIDX_DEV_GEM_1, 85 [59] = XPM_NODEIDX_DEV_GEM_1, 86 [60] = XPM_NODEIDX_DEV_ADMA_0, 87 [61] = XPM_NODEIDX_DEV_ADMA_1, 88 [62] = XPM_NODEIDX_DEV_ADMA_2, 89 [63] = XPM_NODEIDX_DEV_ADMA_3, 90 [64] = XPM_NODEIDX_DEV_ADMA_4, 91 [65] = XPM_NODEIDX_DEV_ADMA_5, 92 [66] = XPM_NODEIDX_DEV_ADMA_6, 93 [67] = XPM_NODEIDX_DEV_ADMA_7, 94 [74] = XPM_NODEIDX_DEV_USB_0, 95 [126] = XPM_NODEIDX_DEV_SDIO_0, 96 [127] = XPM_NODEIDX_DEV_SDIO_0, 97 [128] = XPM_NODEIDX_DEV_SDIO_1, 98 [129] = XPM_NODEIDX_DEV_SDIO_1, 99 [142] = XPM_NODEIDX_DEV_RTC, 100 }; 101 102 /** 103 * irq_to_pm_node_idx - Get PM node index corresponding to the interrupt number 104 * @irq: Interrupt number 105 * 106 * Return: PM node index corresponding to the specified interrupt 107 */ 108 static enum pm_device_node_idx irq_to_pm_node_idx(uint32_t irq) 109 { 110 assert(irq <= IRQ_MAX); 111 return irq_node_map[irq]; 112 } 113 114 /** 115 * pm_client_set_wakeup_sources - Set all devices with enabled interrupts as 116 * wake sources in the LibPM. 117 * @node_id: Node id of processor 118 */ 119 static void pm_client_set_wakeup_sources(uint32_t node_id) 120 { 121 uint32_t reg_num; 122 uint32_t device_id; 123 uint8_t pm_wakeup_nodes_set[XPM_NODEIDX_DEV_MAX]; 124 uintptr_t isenabler1 = PLAT_VERSAL_GICD_BASE + GICD_ISENABLER + 4; 125 126 zeromem(&pm_wakeup_nodes_set, (u_register_t)sizeof(pm_wakeup_nodes_set)); 127 128 for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) { 129 uint32_t base_irq = reg_num << ISENABLER_SHIFT; 130 uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2)); 131 132 if (reg == 0U) { 133 continue; 134 } 135 136 while (reg != 0U) { 137 enum pm_device_node_idx node_idx; 138 uint32_t idx, irq, lowest_set = reg & (-reg); 139 enum pm_ret_status ret; 140 141 idx = __builtin_ctz(lowest_set); 142 irq = base_irq + idx; 143 144 if (irq > IRQ_MAX) { 145 break; 146 } 147 148 node_idx = irq_to_pm_node_idx(irq); 149 reg &= ~lowest_set; 150 151 if (node_idx > XPM_NODEIDX_DEV_MIN && node_idx < XPM_NODEIDX_DEV_MAX) { 152 if (pm_wakeup_nodes_set[node_idx] == 0U) { 153 /* Get device ID from node index */ 154 device_id = PERIPH_DEVID(node_idx); 155 ret = pm_set_wakeup_source(node_id, 156 device_id, 1, 157 SECURE_FLAG); 158 pm_wakeup_nodes_set[node_idx] = (ret == PM_RET_SUCCESS) ? 159 1 : 0; 160 } 161 } 162 } 163 } 164 } 165 166 /** 167 * pm_client_suspend() - Client-specific suspend actions 168 * 169 * This function should contain any PU-specific actions 170 * required prior to sending suspend request to PMU 171 * Actions taken depend on the state system is suspending to. 172 */ 173 void pm_client_suspend(const struct pm_proc *proc, uint32_t state) 174 { 175 bakery_lock_get(&pm_client_secure_lock); 176 177 if (state == PM_STATE_SUSPEND_TO_RAM) { 178 pm_client_set_wakeup_sources((uint32_t)proc->node_id); 179 } 180 181 /* Set powerdown request */ 182 mmio_write_32(FPD_APU_PWRCTL, mmio_read_32(FPD_APU_PWRCTL) | 183 (uint32_t)proc->pwrdn_mask); 184 185 bakery_lock_release(&pm_client_secure_lock); 186 } 187 188 /** 189 * pm_client_abort_suspend() - Client-specific abort-suspend actions 190 * 191 * This function should contain any PU-specific actions 192 * required for aborting a prior suspend request 193 */ 194 void pm_client_abort_suspend(void) 195 { 196 /* Enable interrupts at processor level (for current cpu) */ 197 gicv3_cpuif_enable(plat_my_core_pos()); 198 199 bakery_lock_get(&pm_client_secure_lock); 200 201 /* Clear powerdown request */ 202 mmio_write_32(FPD_APU_PWRCTL, mmio_read_32(FPD_APU_PWRCTL) & 203 ~((uint32_t)primary_proc->pwrdn_mask)); 204 205 bakery_lock_release(&pm_client_secure_lock); 206 } 207 208 /** 209 * pm_get_cpuid() - get the local cpu ID for a global node ID 210 * @nid: node id of the processor 211 * 212 * Return: the cpu ID (starting from 0) for the subsystem 213 */ 214 static uint32_t pm_get_cpuid(uint32_t nid) 215 { 216 for (size_t i = 0U; i < ARRAY_SIZE(pm_procs_all); i++) { 217 if (pm_procs_all[i].node_id == nid) { 218 return i; 219 } 220 } 221 return UNDEFINED_CPUID; 222 } 223 224 /** 225 * pm_client_wakeup() - Client-specific wakeup actions 226 * 227 * This function should contain any PU-specific actions 228 * required for waking up another APU core 229 */ 230 void pm_client_wakeup(const struct pm_proc *proc) 231 { 232 uint32_t cpuid = pm_get_cpuid(proc->node_id); 233 234 if (cpuid == UNDEFINED_CPUID) { 235 return; 236 } 237 238 bakery_lock_get(&pm_client_secure_lock); 239 240 /* clear powerdown bit for affected cpu */ 241 uint32_t val = mmio_read_32(FPD_APU_PWRCTL); 242 val &= ~(proc->pwrdn_mask); 243 mmio_write_32(FPD_APU_PWRCTL, val); 244 245 bakery_lock_release(&pm_client_secure_lock); 246 } 247 248 /** 249 * pm_get_proc() - returns pointer to the proc structure 250 * @cpuid: id of the cpu whose proc struct pointer should be returned 251 * 252 * Return: pointer to a proc structure if proc is found, otherwise NULL 253 */ 254 const struct pm_proc *pm_get_proc(uint32_t cpuid) 255 { 256 if (cpuid < ARRAY_SIZE(pm_procs_all)) { 257 return &pm_procs_all[cpuid]; 258 } 259 260 return NULL; 261 } 262