xref: /rk3399_ARM-atf/plat/xilinx/versal/platform.mk (revision 0b25f4045a19aca9ce5837c8d2703b0bc1dc4e8c)
1*0b25f404SVenkatesh Yadav Abbarapu# Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
2f91c3cb1SSiva Durga Prasad Paladugu#
3f91c3cb1SSiva Durga Prasad Paladugu# SPDX-License-Identifier: BSD-3-Clause
4f91c3cb1SSiva Durga Prasad Paladugu
5f91c3cb1SSiva Durga Prasad Paladuguoverride PROGRAMMABLE_RESET_ADDRESS := 1
6f91c3cb1SSiva Durga Prasad PaladuguPSCI_EXTENDED_STATE_ID := 1
7f91c3cb1SSiva Durga Prasad PaladuguA53_DISABLE_NON_TEMPORAL_HINT := 0
8f91c3cb1SSiva Durga Prasad PaladuguSEPARATE_CODE_AND_RODATA := 1
9f91c3cb1SSiva Durga Prasad Paladuguoverride RESET_TO_BL31 := 1
10f91c3cb1SSiva Durga Prasad PaladuguPL011_GENERIC_UART := 1
11f91c3cb1SSiva Durga Prasad Paladugu
12f91c3cb1SSiva Durga Prasad Paladuguifdef VERSAL_ATF_MEM_BASE
13f91c3cb1SSiva Durga Prasad Paladugu    $(eval $(call add_define,VERSAL_ATF_MEM_BASE))
14f91c3cb1SSiva Durga Prasad Paladugu
15f91c3cb1SSiva Durga Prasad Paladugu    ifndef VERSAL_ATF_MEM_SIZE
16f91c3cb1SSiva Durga Prasad Paladugu        $(error "VERSAL_ATF_BASE defined without VERSAL_ATF_SIZE")
17f91c3cb1SSiva Durga Prasad Paladugu    endif
18f91c3cb1SSiva Durga Prasad Paladugu    $(eval $(call add_define,VERSAL_ATF_MEM_SIZE))
19f91c3cb1SSiva Durga Prasad Paladugu
20f91c3cb1SSiva Durga Prasad Paladugu    ifdef VERSAL_ATF_MEM_PROGBITS_SIZE
21f91c3cb1SSiva Durga Prasad Paladugu        $(eval $(call add_define,VERSAL_ATF_MEM_PROGBITS_SIZE))
22f91c3cb1SSiva Durga Prasad Paladugu    endif
23f91c3cb1SSiva Durga Prasad Paladuguendif
24f91c3cb1SSiva Durga Prasad Paladugu
25f91c3cb1SSiva Durga Prasad Paladuguifdef VERSAL_BL32_MEM_BASE
26f91c3cb1SSiva Durga Prasad Paladugu    $(eval $(call add_define,VERSAL_BL32_MEM_BASE))
27f91c3cb1SSiva Durga Prasad Paladugu
28f91c3cb1SSiva Durga Prasad Paladugu    ifndef VERSAL_BL32_MEM_SIZE
29f91c3cb1SSiva Durga Prasad Paladugu        $(error "VERSAL_BL32_BASE defined without VERSAL_BL32_SIZE")
30f91c3cb1SSiva Durga Prasad Paladugu    endif
31f91c3cb1SSiva Durga Prasad Paladugu    $(eval $(call add_define,VERSAL_BL32_MEM_SIZE))
32f91c3cb1SSiva Durga Prasad Paladuguendif
33f91c3cb1SSiva Durga Prasad Paladugu
347b9f0cfdSSiva Durga Prasad PaladuguVERSAL_PLATFORM ?= silicon
35f91c3cb1SSiva Durga Prasad Paladugu$(eval $(call add_define_val,VERSAL_PLATFORM,VERSAL_PLATFORM_ID_${VERSAL_PLATFORM}))
36f91c3cb1SSiva Durga Prasad Paladugu
375a8ffeabSTejas PatelPLAT_INCLUDES		:=	-Iinclude/plat/arm/common/			\
385a8ffeabSTejas Patel				-Iplat/xilinx/common/include/			\
396e2f0d10SWendy Liang				-Iplat/xilinx/common/ipi_mailbox_service/	\
40c73a90e5STejas Patel				-Iplat/xilinx/versal/include/			\
41c73a90e5STejas Patel				-Iplat/xilinx/versal/pm_service/
42f91c3cb1SSiva Durga Prasad Paladugu
43a6ea06f5SAlexei Fedorov# Include GICv3 driver files
44a6ea06f5SAlexei Fedorovinclude drivers/arm/gic/v3/gicv3.mk
45a6ea06f5SAlexei Fedorov
46f91c3cb1SSiva Durga Prasad PaladuguPLAT_BL_COMMON_SOURCES	:=	lib/xlat_tables/xlat_tables_common.c		\
47f91c3cb1SSiva Durga Prasad Paladugu				lib/xlat_tables/aarch64/xlat_tables.c		\
48*0b25f404SVenkatesh Yadav Abbarapu				drivers/arm/dcc/dcc_console.c			\
49f91c3cb1SSiva Durga Prasad Paladugu				drivers/delay_timer/delay_timer.c		\
50f91c3cb1SSiva Durga Prasad Paladugu				drivers/delay_timer/generic_delay_timer.c	\
51a6ea06f5SAlexei Fedorov				${GICV3_SOURCES}				\
52f91c3cb1SSiva Durga Prasad Paladugu				drivers/arm/pl011/aarch64/pl011_console.S	\
532cc97771SAmbroise Vincent				plat/common/aarch64/crash_console_helpers.S	\
545a8ffeabSTejas Patel				plat/arm/common/arm_cci.c			\
5531ce893eSVenkatesh Yadav Abbarapu				plat/arm/common/arm_common.c			\
56f91c3cb1SSiva Durga Prasad Paladugu				plat/common/plat_gicv3.c			\
57f91c3cb1SSiva Durga Prasad Paladugu				plat/xilinx/versal/aarch64/versal_helpers.S	\
58f91c3cb1SSiva Durga Prasad Paladugu				plat/xilinx/versal/aarch64/versal_common.c
59f91c3cb1SSiva Durga Prasad Paladugu
60*0b25f404SVenkatesh Yadav AbbarapuVERSAL_CONSOLE	?=	pl011
61*0b25f404SVenkatesh Yadav Abbarapuifeq (${VERSAL_CONSOLE}, $(filter ${VERSAL_CONSOLE},pl011 pl011_0 pl011_1 dcc))
62*0b25f404SVenkatesh Yadav Abbarapuelse
63*0b25f404SVenkatesh Yadav Abbarapu  $(error "Please define VERSAL_CONSOLE")
64*0b25f404SVenkatesh Yadav Abbarapuendif
65*0b25f404SVenkatesh Yadav Abbarapu
66*0b25f404SVenkatesh Yadav Abbarapu$(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE}))
67*0b25f404SVenkatesh Yadav Abbarapu
685a8ffeabSTejas PatelBL31_SOURCES		+=	drivers/arm/cci/cci.c				\
69f91c3cb1SSiva Durga Prasad Paladugu				lib/cpus/aarch64/cortex_a72.S			\
70f91c3cb1SSiva Durga Prasad Paladugu				plat/common/plat_psci_common.c			\
71c73a90e5STejas Patel				plat/xilinx/common/ipi.c			\
7231ce893eSVenkatesh Yadav Abbarapu				plat/xilinx/common/plat_startup.c		\
736e2f0d10SWendy Liang				plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
74c73a90e5STejas Patel				plat/xilinx/common/pm_service/pm_ipi.c		\
75f91c3cb1SSiva Durga Prasad Paladugu				plat/xilinx/versal/bl31_versal_setup.c		\
76f91c3cb1SSiva Durga Prasad Paladugu				plat/xilinx/versal/plat_psci.c			\
77f91c3cb1SSiva Durga Prasad Paladugu				plat/xilinx/versal/plat_versal.c		\
78f91c3cb1SSiva Durga Prasad Paladugu				plat/xilinx/versal/plat_topology.c		\
79f91c3cb1SSiva Durga Prasad Paladugu				plat/xilinx/versal/sip_svc_setup.c		\
80c73a90e5STejas Patel				plat/xilinx/versal/versal_gicv3.c		\
81c73a90e5STejas Patel				plat/xilinx/versal/versal_ipi.c			\
82c73a90e5STejas Patel				plat/xilinx/versal/pm_service/pm_svc_main.c	\
8395794c73STejas Patel				plat/xilinx/versal/pm_service/pm_api_sys.c	\
84c73a90e5STejas Patel				plat/xilinx/versal/pm_service/pm_client.c
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