1f91c3cb1SSiva Durga Prasad Paladugu /* 2619bc13eSMichal Simek * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3*de7ed953SPrasad Kummari * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4f91c3cb1SSiva Durga Prasad Paladugu * 5f91c3cb1SSiva Durga Prasad Paladugu * SPDX-License-Identifier: BSD-3-Clause 6f91c3cb1SSiva Durga Prasad Paladugu */ 7f91c3cb1SSiva Durga Prasad Paladugu 85a8ffeabSTejas Patel #include <assert.h> 95a8ffeabSTejas Patel #include <plat_arm.h> 10d4821739STejas Patel #include <plat_private.h> 11394a65aaSTejas Patel #include <pm_common.h> 1209d40e0eSAntonio Nino Diaz #include <common/debug.h> 1309d40e0eSAntonio Nino Diaz #include <lib/mmio.h> 1409d40e0eSAntonio Nino Diaz #include <lib/psci/psci.h> 1509d40e0eSAntonio Nino Diaz #include <plat/common/platform.h> 160abf4bbaSSaeed Nowshadi #include <plat/arm/common/plat_arm.h> 1709d40e0eSAntonio Nino Diaz 18394a65aaSTejas Patel #include "pm_api_sys.h" 19394a65aaSTejas Patel #include "pm_client.h" 20394a65aaSTejas Patel 21f91c3cb1SSiva Durga Prasad Paladugu static uintptr_t versal_sec_entry; 22f91c3cb1SSiva Durga Prasad Paladugu 23912b7a6fSVenkatesh Yadav Abbarapu static int32_t versal_pwr_domain_on(u_register_t mpidr) 24f91c3cb1SSiva Durga Prasad Paladugu { 25912b7a6fSVenkatesh Yadav Abbarapu int32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 26394a65aaSTejas Patel const struct pm_proc *proc; 27f91c3cb1SSiva Durga Prasad Paladugu 28f91c3cb1SSiva Durga Prasad Paladugu VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); 29f91c3cb1SSiva Durga Prasad Paladugu 30b9fa2d9fSAbhyuday Godhasara if (cpu_id == -1) { 31f91c3cb1SSiva Durga Prasad Paladugu return PSCI_E_INTERN_FAIL; 32b9fa2d9fSAbhyuday Godhasara } 33f91c3cb1SSiva Durga Prasad Paladugu 34912b7a6fSVenkatesh Yadav Abbarapu proc = pm_get_proc((uint32_t)cpu_id); 35f91c3cb1SSiva Durga Prasad Paladugu 36394a65aaSTejas Patel /* Send request to PMC to wake up selected ACPU core */ 37526a1fd1SAbhyuday Godhasara (void)pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFFU) | 0x1U, 384697164aSTejas Patel versal_sec_entry >> 32, 0, SECURE_FLAG); 39f91c3cb1SSiva Durga Prasad Paladugu 40394a65aaSTejas Patel /* Clear power down request */ 41394a65aaSTejas Patel pm_client_wakeup(proc); 42f91c3cb1SSiva Durga Prasad Paladugu 43f91c3cb1SSiva Durga Prasad Paladugu return PSCI_E_SUCCESS; 44f91c3cb1SSiva Durga Prasad Paladugu } 45f91c3cb1SSiva Durga Prasad Paladugu 465a8ffeabSTejas Patel /** 475a8ffeabSTejas Patel * versal_pwr_domain_suspend() - This function sends request to PMC to suspend 485a8ffeabSTejas Patel * core. 49*de7ed953SPrasad Kummari * @target_state: Targated state. 505a8ffeabSTejas Patel * 515a8ffeabSTejas Patel */ 525a8ffeabSTejas Patel static void versal_pwr_domain_suspend(const psci_power_state_t *target_state) 535a8ffeabSTejas Patel { 54912b7a6fSVenkatesh Yadav Abbarapu uint32_t state; 55912b7a6fSVenkatesh Yadav Abbarapu uint32_t cpu_id = plat_my_core_pos(); 565a8ffeabSTejas Patel const struct pm_proc *proc = pm_get_proc(cpu_id); 575a8ffeabSTejas Patel 580623dceaSAbhyuday Godhasara for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { 595a8ffeabSTejas Patel VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 605a8ffeabSTejas Patel __func__, i, target_state->pwr_domain_state[i]); 61b9fa2d9fSAbhyuday Godhasara } 625a8ffeabSTejas Patel 635a8ffeabSTejas Patel plat_versal_gic_cpuif_disable(); 645a8ffeabSTejas Patel 65d4c7b550SRavi Patel if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 665a8ffeabSTejas Patel plat_versal_gic_save(); 67d4c7b550SRavi Patel } 685a8ffeabSTejas Patel 695a8ffeabSTejas Patel state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? 705a8ffeabSTejas Patel PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE; 715a8ffeabSTejas Patel 725a8ffeabSTejas Patel /* Send request to PMC to suspend this core */ 73526a1fd1SAbhyuday Godhasara (void)pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_sec_entry, 744697164aSTejas Patel SECURE_FLAG); 755a8ffeabSTejas Patel 765a8ffeabSTejas Patel /* APU is to be turned off */ 775a8ffeabSTejas Patel if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 785a8ffeabSTejas Patel /* disable coherency */ 795a8ffeabSTejas Patel plat_arm_interconnect_exit_coherency(); 805a8ffeabSTejas Patel } 815a8ffeabSTejas Patel } 825a8ffeabSTejas Patel 835a8ffeabSTejas Patel /** 845a8ffeabSTejas Patel * versal_pwr_domain_suspend_finish() - This function performs actions to finish 855a8ffeabSTejas Patel * suspend procedure. 86*de7ed953SPrasad Kummari * @target_state: Targated state. 875a8ffeabSTejas Patel * 885a8ffeabSTejas Patel */ 895a8ffeabSTejas Patel static void versal_pwr_domain_suspend_finish( 905a8ffeabSTejas Patel const psci_power_state_t *target_state) 915a8ffeabSTejas Patel { 92912b7a6fSVenkatesh Yadav Abbarapu uint32_t cpu_id = plat_my_core_pos(); 935a8ffeabSTejas Patel const struct pm_proc *proc = pm_get_proc(cpu_id); 945a8ffeabSTejas Patel 950623dceaSAbhyuday Godhasara for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { 965a8ffeabSTejas Patel VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 975a8ffeabSTejas Patel __func__, i, target_state->pwr_domain_state[i]); 98b9fa2d9fSAbhyuday Godhasara } 995a8ffeabSTejas Patel 1005a8ffeabSTejas Patel /* Clear the APU power control register for this cpu */ 1015a8ffeabSTejas Patel pm_client_wakeup(proc); 1025a8ffeabSTejas Patel 1035a8ffeabSTejas Patel /* enable coherency */ 1045a8ffeabSTejas Patel plat_arm_interconnect_enter_coherency(); 1055a8ffeabSTejas Patel 1065a8ffeabSTejas Patel /* APU was turned off, so restore GIC context */ 1075a8ffeabSTejas Patel if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 1085a8ffeabSTejas Patel plat_versal_gic_resume(); 1095a8ffeabSTejas Patel } 110d4c7b550SRavi Patel 111d4c7b550SRavi Patel plat_versal_gic_cpuif_enable(); 1125a8ffeabSTejas Patel } 1135a8ffeabSTejas Patel 114f91c3cb1SSiva Durga Prasad Paladugu void versal_pwr_domain_on_finish(const psci_power_state_t *target_state) 115f91c3cb1SSiva Durga Prasad Paladugu { 116f91c3cb1SSiva Durga Prasad Paladugu /* Enable the gic cpu interface */ 117f91c3cb1SSiva Durga Prasad Paladugu plat_versal_gic_pcpu_init(); 118f91c3cb1SSiva Durga Prasad Paladugu 119f91c3cb1SSiva Durga Prasad Paladugu /* Program the gic per-cpu distributor or re-distributor interface */ 120f91c3cb1SSiva Durga Prasad Paladugu plat_versal_gic_cpuif_enable(); 121f91c3cb1SSiva Durga Prasad Paladugu } 122f91c3cb1SSiva Durga Prasad Paladugu 1235a8ffeabSTejas Patel /** 124*de7ed953SPrasad Kummari * versal_system_off() - This function sends the system off request to firmware. 125*de7ed953SPrasad Kummari * This function does not return. 126*de7ed953SPrasad Kummari * 1270abf4bbaSSaeed Nowshadi */ 1280abf4bbaSSaeed Nowshadi static void __dead2 versal_system_off(void) 1290abf4bbaSSaeed Nowshadi { 1300abf4bbaSSaeed Nowshadi /* Send the power down request to the PMC */ 131526a1fd1SAbhyuday Godhasara (void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN, 1324697164aSTejas Patel pm_get_shutdown_scope(), SECURE_FLAG); 1330abf4bbaSSaeed Nowshadi 134b9fa2d9fSAbhyuday Godhasara while (1) { 1350abf4bbaSSaeed Nowshadi wfi(); 1360abf4bbaSSaeed Nowshadi } 137b9fa2d9fSAbhyuday Godhasara } 1380abf4bbaSSaeed Nowshadi 1390abf4bbaSSaeed Nowshadi /** 140*de7ed953SPrasad Kummari * versal_system_reset() - This function sends the reset request to firmware 141*de7ed953SPrasad Kummari * for the system to reset. This function does not 142*de7ed953SPrasad Kummari * return. 143*de7ed953SPrasad Kummari * 1440abf4bbaSSaeed Nowshadi */ 1450abf4bbaSSaeed Nowshadi static void __dead2 versal_system_reset(void) 1460abf4bbaSSaeed Nowshadi { 1470abf4bbaSSaeed Nowshadi /* Send the system reset request to the PMC */ 148526a1fd1SAbhyuday Godhasara (void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET, 1494697164aSTejas Patel pm_get_shutdown_scope(), SECURE_FLAG); 1500abf4bbaSSaeed Nowshadi 151b9fa2d9fSAbhyuday Godhasara while (1) { 1520abf4bbaSSaeed Nowshadi wfi(); 1530abf4bbaSSaeed Nowshadi } 154b9fa2d9fSAbhyuday Godhasara } 1550abf4bbaSSaeed Nowshadi 1560abf4bbaSSaeed Nowshadi /** 157*de7ed953SPrasad Kummari * versal_pwr_domain_off() - This function performs actions to turn off core. 158*de7ed953SPrasad Kummari * @target_state: Targated state. 1595a8ffeabSTejas Patel * 1605a8ffeabSTejas Patel */ 1615a8ffeabSTejas Patel static void versal_pwr_domain_off(const psci_power_state_t *target_state) 1625a8ffeabSTejas Patel { 163912b7a6fSVenkatesh Yadav Abbarapu uint32_t cpu_id = plat_my_core_pos(); 1645a8ffeabSTejas Patel const struct pm_proc *proc = pm_get_proc(cpu_id); 1655a8ffeabSTejas Patel 1660623dceaSAbhyuday Godhasara for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { 1675a8ffeabSTejas Patel VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 1685a8ffeabSTejas Patel __func__, i, target_state->pwr_domain_state[i]); 169b9fa2d9fSAbhyuday Godhasara } 1705a8ffeabSTejas Patel 1715a8ffeabSTejas Patel /* Prevent interrupts from spuriously waking up this cpu */ 1725a8ffeabSTejas Patel plat_versal_gic_cpuif_disable(); 1735a8ffeabSTejas Patel 1745a8ffeabSTejas Patel /* 1755a8ffeabSTejas Patel * Send request to PMC to power down the appropriate APU CPU 1765a8ffeabSTejas Patel * core. 1775a8ffeabSTejas Patel * According to PSCI specification, CPU_off function does not 1785a8ffeabSTejas Patel * have resume address and CPU core can only be woken up 1795a8ffeabSTejas Patel * invoking CPU_on function, during which resume address will 1805a8ffeabSTejas Patel * be set. 1815a8ffeabSTejas Patel */ 182526a1fd1SAbhyuday Godhasara (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0, 1834697164aSTejas Patel SECURE_FLAG); 1845a8ffeabSTejas Patel } 1855a8ffeabSTejas Patel 1865a8ffeabSTejas Patel /** 1875a8ffeabSTejas Patel * versal_validate_power_state() - This function ensures that the power state 1885a8ffeabSTejas Patel * parameter in request is valid. 189*de7ed953SPrasad Kummari * @power_state: Power state of core. 190*de7ed953SPrasad Kummari * @req_state: Requested state. 1915a8ffeabSTejas Patel * 192*de7ed953SPrasad Kummari * Return: Returns status, either success or reason. 1935a8ffeabSTejas Patel * 1945a8ffeabSTejas Patel */ 195912b7a6fSVenkatesh Yadav Abbarapu static int32_t versal_validate_power_state(uint32_t power_state, 1965a8ffeabSTejas Patel psci_power_state_t *req_state) 1975a8ffeabSTejas Patel { 1985a8ffeabSTejas Patel VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); 1995a8ffeabSTejas Patel 200912b7a6fSVenkatesh Yadav Abbarapu uint32_t pstate = psci_get_pstate_type(power_state); 2015a8ffeabSTejas Patel 2025a8ffeabSTejas Patel assert(req_state); 2035a8ffeabSTejas Patel 2045a8ffeabSTejas Patel /* Sanity check the requested state */ 205b9fa2d9fSAbhyuday Godhasara if (pstate == PSTATE_TYPE_STANDBY) { 2065a8ffeabSTejas Patel req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; 207b9fa2d9fSAbhyuday Godhasara } else { 2085a8ffeabSTejas Patel req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 209b9fa2d9fSAbhyuday Godhasara } 2105a8ffeabSTejas Patel 2115a8ffeabSTejas Patel /* We expect the 'state id' to be zero */ 212a62c40d4SAbhyuday Godhasara if (psci_get_pstate_id(power_state) != 0U) { 2135a8ffeabSTejas Patel return PSCI_E_INVALID_PARAMS; 214b9fa2d9fSAbhyuday Godhasara } 2155a8ffeabSTejas Patel 2165a8ffeabSTejas Patel return PSCI_E_SUCCESS; 2175a8ffeabSTejas Patel } 2185a8ffeabSTejas Patel 2195a8ffeabSTejas Patel /** 220*de7ed953SPrasad Kummari * versal_get_sys_suspend_power_state() - Get power state for system suspend. 221*de7ed953SPrasad Kummari * @req_state: Requested state. 2225a8ffeabSTejas Patel * 2235a8ffeabSTejas Patel */ 2245a8ffeabSTejas Patel static void versal_get_sys_suspend_power_state(psci_power_state_t *req_state) 2255a8ffeabSTejas Patel { 2265a8ffeabSTejas Patel req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; 2275a8ffeabSTejas Patel req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; 2285a8ffeabSTejas Patel } 2295a8ffeabSTejas Patel 230f91c3cb1SSiva Durga Prasad Paladugu static const struct plat_psci_ops versal_nopmc_psci_ops = { 231394a65aaSTejas Patel .pwr_domain_on = versal_pwr_domain_on, 2325a8ffeabSTejas Patel .pwr_domain_off = versal_pwr_domain_off, 233f91c3cb1SSiva Durga Prasad Paladugu .pwr_domain_on_finish = versal_pwr_domain_on_finish, 2345a8ffeabSTejas Patel .pwr_domain_suspend = versal_pwr_domain_suspend, 2355a8ffeabSTejas Patel .pwr_domain_suspend_finish = versal_pwr_domain_suspend_finish, 2360abf4bbaSSaeed Nowshadi .system_off = versal_system_off, 2370abf4bbaSSaeed Nowshadi .system_reset = versal_system_reset, 2385a8ffeabSTejas Patel .validate_power_state = versal_validate_power_state, 2395a8ffeabSTejas Patel .get_sys_suspend_power_state = versal_get_sys_suspend_power_state, 240f91c3cb1SSiva Durga Prasad Paladugu }; 241f91c3cb1SSiva Durga Prasad Paladugu 242f91c3cb1SSiva Durga Prasad Paladugu /******************************************************************************* 243f91c3cb1SSiva Durga Prasad Paladugu * Export the platform specific power ops. 244f91c3cb1SSiva Durga Prasad Paladugu ******************************************************************************/ 245f7c48d9eSVenkatesh Yadav Abbarapu int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint, 246f91c3cb1SSiva Durga Prasad Paladugu const struct plat_psci_ops **psci_ops) 247f91c3cb1SSiva Durga Prasad Paladugu { 248f91c3cb1SSiva Durga Prasad Paladugu versal_sec_entry = sec_entrypoint; 249f91c3cb1SSiva Durga Prasad Paladugu 250f91c3cb1SSiva Durga Prasad Paladugu *psci_ops = &versal_nopmc_psci_ops; 251f91c3cb1SSiva Durga Prasad Paladugu 252f91c3cb1SSiva Durga Prasad Paladugu return 0; 253f91c3cb1SSiva Durga Prasad Paladugu } 254