1f91c3cb1SSiva Durga Prasad Paladugu /* 2619bc13eSMichal Simek * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3de7ed953SPrasad Kummari * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4f91c3cb1SSiva Durga Prasad Paladugu * 5f91c3cb1SSiva Durga Prasad Paladugu * SPDX-License-Identifier: BSD-3-Clause 6f91c3cb1SSiva Durga Prasad Paladugu */ 7f91c3cb1SSiva Durga Prasad Paladugu 85a8ffeabSTejas Patel #include <assert.h> 9*01a326abSPrasad Kummari 1009d40e0eSAntonio Nino Diaz #include <common/debug.h> 1109d40e0eSAntonio Nino Diaz #include <lib/mmio.h> 1209d40e0eSAntonio Nino Diaz #include <lib/psci/psci.h> 130abf4bbaSSaeed Nowshadi #include <plat/arm/common/plat_arm.h> 14*01a326abSPrasad Kummari #include <plat/common/platform.h> 15*01a326abSPrasad Kummari #include <plat_arm.h> 1609d40e0eSAntonio Nino Diaz 17*01a326abSPrasad Kummari #include <plat_private.h> 18394a65aaSTejas Patel #include "pm_api_sys.h" 19394a65aaSTejas Patel #include "pm_client.h" 20*01a326abSPrasad Kummari #include <pm_common.h> 21394a65aaSTejas Patel 22f91c3cb1SSiva Durga Prasad Paladugu static uintptr_t versal_sec_entry; 23f91c3cb1SSiva Durga Prasad Paladugu 24912b7a6fSVenkatesh Yadav Abbarapu static int32_t versal_pwr_domain_on(u_register_t mpidr) 25f91c3cb1SSiva Durga Prasad Paladugu { 26912b7a6fSVenkatesh Yadav Abbarapu int32_t cpu_id = plat_core_pos_by_mpidr(mpidr); 27394a65aaSTejas Patel const struct pm_proc *proc; 28f91c3cb1SSiva Durga Prasad Paladugu 29f91c3cb1SSiva Durga Prasad Paladugu VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); 30f91c3cb1SSiva Durga Prasad Paladugu 31b9fa2d9fSAbhyuday Godhasara if (cpu_id == -1) { 32f91c3cb1SSiva Durga Prasad Paladugu return PSCI_E_INTERN_FAIL; 33b9fa2d9fSAbhyuday Godhasara } 34f91c3cb1SSiva Durga Prasad Paladugu 35912b7a6fSVenkatesh Yadav Abbarapu proc = pm_get_proc((uint32_t)cpu_id); 36f91c3cb1SSiva Durga Prasad Paladugu 37394a65aaSTejas Patel /* Send request to PMC to wake up selected ACPU core */ 38526a1fd1SAbhyuday Godhasara (void)pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFFU) | 0x1U, 394697164aSTejas Patel versal_sec_entry >> 32, 0, SECURE_FLAG); 40f91c3cb1SSiva Durga Prasad Paladugu 41394a65aaSTejas Patel /* Clear power down request */ 42394a65aaSTejas Patel pm_client_wakeup(proc); 43f91c3cb1SSiva Durga Prasad Paladugu 44f91c3cb1SSiva Durga Prasad Paladugu return PSCI_E_SUCCESS; 45f91c3cb1SSiva Durga Prasad Paladugu } 46f91c3cb1SSiva Durga Prasad Paladugu 475a8ffeabSTejas Patel /** 485a8ffeabSTejas Patel * versal_pwr_domain_suspend() - This function sends request to PMC to suspend 495a8ffeabSTejas Patel * core. 50de7ed953SPrasad Kummari * @target_state: Targated state. 515a8ffeabSTejas Patel * 525a8ffeabSTejas Patel */ 535a8ffeabSTejas Patel static void versal_pwr_domain_suspend(const psci_power_state_t *target_state) 545a8ffeabSTejas Patel { 55912b7a6fSVenkatesh Yadav Abbarapu uint32_t state; 56912b7a6fSVenkatesh Yadav Abbarapu uint32_t cpu_id = plat_my_core_pos(); 575a8ffeabSTejas Patel const struct pm_proc *proc = pm_get_proc(cpu_id); 585a8ffeabSTejas Patel 590623dceaSAbhyuday Godhasara for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { 605a8ffeabSTejas Patel VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 615a8ffeabSTejas Patel __func__, i, target_state->pwr_domain_state[i]); 62b9fa2d9fSAbhyuday Godhasara } 635a8ffeabSTejas Patel 645a8ffeabSTejas Patel plat_versal_gic_cpuif_disable(); 655a8ffeabSTejas Patel 66d4c7b550SRavi Patel if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 675a8ffeabSTejas Patel plat_versal_gic_save(); 68d4c7b550SRavi Patel } 695a8ffeabSTejas Patel 705a8ffeabSTejas Patel state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? 715a8ffeabSTejas Patel PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE; 725a8ffeabSTejas Patel 735a8ffeabSTejas Patel /* Send request to PMC to suspend this core */ 74526a1fd1SAbhyuday Godhasara (void)pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_sec_entry, 754697164aSTejas Patel SECURE_FLAG); 765a8ffeabSTejas Patel 775a8ffeabSTejas Patel /* APU is to be turned off */ 785a8ffeabSTejas Patel if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 795a8ffeabSTejas Patel /* disable coherency */ 805a8ffeabSTejas Patel plat_arm_interconnect_exit_coherency(); 815a8ffeabSTejas Patel } 825a8ffeabSTejas Patel } 835a8ffeabSTejas Patel 845a8ffeabSTejas Patel /** 855a8ffeabSTejas Patel * versal_pwr_domain_suspend_finish() - This function performs actions to finish 865a8ffeabSTejas Patel * suspend procedure. 87de7ed953SPrasad Kummari * @target_state: Targated state. 885a8ffeabSTejas Patel * 895a8ffeabSTejas Patel */ 905a8ffeabSTejas Patel static void versal_pwr_domain_suspend_finish( 915a8ffeabSTejas Patel const psci_power_state_t *target_state) 925a8ffeabSTejas Patel { 93912b7a6fSVenkatesh Yadav Abbarapu uint32_t cpu_id = plat_my_core_pos(); 945a8ffeabSTejas Patel const struct pm_proc *proc = pm_get_proc(cpu_id); 955a8ffeabSTejas Patel 960623dceaSAbhyuday Godhasara for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { 975a8ffeabSTejas Patel VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 985a8ffeabSTejas Patel __func__, i, target_state->pwr_domain_state[i]); 99b9fa2d9fSAbhyuday Godhasara } 1005a8ffeabSTejas Patel 1015a8ffeabSTejas Patel /* Clear the APU power control register for this cpu */ 1025a8ffeabSTejas Patel pm_client_wakeup(proc); 1035a8ffeabSTejas Patel 1045a8ffeabSTejas Patel /* enable coherency */ 1055a8ffeabSTejas Patel plat_arm_interconnect_enter_coherency(); 1065a8ffeabSTejas Patel 1075a8ffeabSTejas Patel /* APU was turned off, so restore GIC context */ 1085a8ffeabSTejas Patel if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 1095a8ffeabSTejas Patel plat_versal_gic_resume(); 1105a8ffeabSTejas Patel } 111d4c7b550SRavi Patel 112d4c7b550SRavi Patel plat_versal_gic_cpuif_enable(); 1135a8ffeabSTejas Patel } 1145a8ffeabSTejas Patel 115f91c3cb1SSiva Durga Prasad Paladugu void versal_pwr_domain_on_finish(const psci_power_state_t *target_state) 116f91c3cb1SSiva Durga Prasad Paladugu { 117f91c3cb1SSiva Durga Prasad Paladugu /* Enable the gic cpu interface */ 118f91c3cb1SSiva Durga Prasad Paladugu plat_versal_gic_pcpu_init(); 119f91c3cb1SSiva Durga Prasad Paladugu 120f91c3cb1SSiva Durga Prasad Paladugu /* Program the gic per-cpu distributor or re-distributor interface */ 121f91c3cb1SSiva Durga Prasad Paladugu plat_versal_gic_cpuif_enable(); 122f91c3cb1SSiva Durga Prasad Paladugu } 123f91c3cb1SSiva Durga Prasad Paladugu 1245a8ffeabSTejas Patel /** 125de7ed953SPrasad Kummari * versal_system_off() - This function sends the system off request to firmware. 126de7ed953SPrasad Kummari * This function does not return. 127de7ed953SPrasad Kummari * 1280abf4bbaSSaeed Nowshadi */ 1290abf4bbaSSaeed Nowshadi static void __dead2 versal_system_off(void) 1300abf4bbaSSaeed Nowshadi { 1310abf4bbaSSaeed Nowshadi /* Send the power down request to the PMC */ 132526a1fd1SAbhyuday Godhasara (void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN, 1334697164aSTejas Patel pm_get_shutdown_scope(), SECURE_FLAG); 1340abf4bbaSSaeed Nowshadi 135b9fa2d9fSAbhyuday Godhasara while (1) { 1360abf4bbaSSaeed Nowshadi wfi(); 1370abf4bbaSSaeed Nowshadi } 138b9fa2d9fSAbhyuday Godhasara } 1390abf4bbaSSaeed Nowshadi 1400abf4bbaSSaeed Nowshadi /** 141de7ed953SPrasad Kummari * versal_system_reset() - This function sends the reset request to firmware 142de7ed953SPrasad Kummari * for the system to reset. This function does not 143de7ed953SPrasad Kummari * return. 144de7ed953SPrasad Kummari * 1450abf4bbaSSaeed Nowshadi */ 1460abf4bbaSSaeed Nowshadi static void __dead2 versal_system_reset(void) 1470abf4bbaSSaeed Nowshadi { 1480abf4bbaSSaeed Nowshadi /* Send the system reset request to the PMC */ 149526a1fd1SAbhyuday Godhasara (void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET, 1504697164aSTejas Patel pm_get_shutdown_scope(), SECURE_FLAG); 1510abf4bbaSSaeed Nowshadi 152b9fa2d9fSAbhyuday Godhasara while (1) { 1530abf4bbaSSaeed Nowshadi wfi(); 1540abf4bbaSSaeed Nowshadi } 155b9fa2d9fSAbhyuday Godhasara } 1560abf4bbaSSaeed Nowshadi 1570abf4bbaSSaeed Nowshadi /** 158de7ed953SPrasad Kummari * versal_pwr_domain_off() - This function performs actions to turn off core. 159de7ed953SPrasad Kummari * @target_state: Targated state. 1605a8ffeabSTejas Patel * 1615a8ffeabSTejas Patel */ 1625a8ffeabSTejas Patel static void versal_pwr_domain_off(const psci_power_state_t *target_state) 1635a8ffeabSTejas Patel { 164912b7a6fSVenkatesh Yadav Abbarapu uint32_t cpu_id = plat_my_core_pos(); 1655a8ffeabSTejas Patel const struct pm_proc *proc = pm_get_proc(cpu_id); 1665a8ffeabSTejas Patel 1670623dceaSAbhyuday Godhasara for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) { 1685a8ffeabSTejas Patel VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 1695a8ffeabSTejas Patel __func__, i, target_state->pwr_domain_state[i]); 170b9fa2d9fSAbhyuday Godhasara } 1715a8ffeabSTejas Patel 1725a8ffeabSTejas Patel /* Prevent interrupts from spuriously waking up this cpu */ 1735a8ffeabSTejas Patel plat_versal_gic_cpuif_disable(); 1745a8ffeabSTejas Patel 1755a8ffeabSTejas Patel /* 1765a8ffeabSTejas Patel * Send request to PMC to power down the appropriate APU CPU 1775a8ffeabSTejas Patel * core. 1785a8ffeabSTejas Patel * According to PSCI specification, CPU_off function does not 1795a8ffeabSTejas Patel * have resume address and CPU core can only be woken up 1805a8ffeabSTejas Patel * invoking CPU_on function, during which resume address will 1815a8ffeabSTejas Patel * be set. 1825a8ffeabSTejas Patel */ 183526a1fd1SAbhyuday Godhasara (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0, 1844697164aSTejas Patel SECURE_FLAG); 1855a8ffeabSTejas Patel } 1865a8ffeabSTejas Patel 1875a8ffeabSTejas Patel /** 1885a8ffeabSTejas Patel * versal_validate_power_state() - This function ensures that the power state 1895a8ffeabSTejas Patel * parameter in request is valid. 190de7ed953SPrasad Kummari * @power_state: Power state of core. 191de7ed953SPrasad Kummari * @req_state: Requested state. 1925a8ffeabSTejas Patel * 193de7ed953SPrasad Kummari * Return: Returns status, either success or reason. 1945a8ffeabSTejas Patel * 1955a8ffeabSTejas Patel */ 196912b7a6fSVenkatesh Yadav Abbarapu static int32_t versal_validate_power_state(uint32_t power_state, 1975a8ffeabSTejas Patel psci_power_state_t *req_state) 1985a8ffeabSTejas Patel { 1995a8ffeabSTejas Patel VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); 2005a8ffeabSTejas Patel 201912b7a6fSVenkatesh Yadav Abbarapu uint32_t pstate = psci_get_pstate_type(power_state); 2025a8ffeabSTejas Patel 2035a8ffeabSTejas Patel assert(req_state); 2045a8ffeabSTejas Patel 2055a8ffeabSTejas Patel /* Sanity check the requested state */ 206b9fa2d9fSAbhyuday Godhasara if (pstate == PSTATE_TYPE_STANDBY) { 2075a8ffeabSTejas Patel req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; 208b9fa2d9fSAbhyuday Godhasara } else { 2095a8ffeabSTejas Patel req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 210b9fa2d9fSAbhyuday Godhasara } 2115a8ffeabSTejas Patel 2125a8ffeabSTejas Patel /* We expect the 'state id' to be zero */ 213a62c40d4SAbhyuday Godhasara if (psci_get_pstate_id(power_state) != 0U) { 2145a8ffeabSTejas Patel return PSCI_E_INVALID_PARAMS; 215b9fa2d9fSAbhyuday Godhasara } 2165a8ffeabSTejas Patel 2175a8ffeabSTejas Patel return PSCI_E_SUCCESS; 2185a8ffeabSTejas Patel } 2195a8ffeabSTejas Patel 2205a8ffeabSTejas Patel /** 221de7ed953SPrasad Kummari * versal_get_sys_suspend_power_state() - Get power state for system suspend. 222de7ed953SPrasad Kummari * @req_state: Requested state. 2235a8ffeabSTejas Patel * 2245a8ffeabSTejas Patel */ 2255a8ffeabSTejas Patel static void versal_get_sys_suspend_power_state(psci_power_state_t *req_state) 2265a8ffeabSTejas Patel { 2275a8ffeabSTejas Patel req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; 2285a8ffeabSTejas Patel req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; 2295a8ffeabSTejas Patel } 2305a8ffeabSTejas Patel 231f91c3cb1SSiva Durga Prasad Paladugu static const struct plat_psci_ops versal_nopmc_psci_ops = { 232394a65aaSTejas Patel .pwr_domain_on = versal_pwr_domain_on, 2335a8ffeabSTejas Patel .pwr_domain_off = versal_pwr_domain_off, 234f91c3cb1SSiva Durga Prasad Paladugu .pwr_domain_on_finish = versal_pwr_domain_on_finish, 2355a8ffeabSTejas Patel .pwr_domain_suspend = versal_pwr_domain_suspend, 2365a8ffeabSTejas Patel .pwr_domain_suspend_finish = versal_pwr_domain_suspend_finish, 2370abf4bbaSSaeed Nowshadi .system_off = versal_system_off, 2380abf4bbaSSaeed Nowshadi .system_reset = versal_system_reset, 2395a8ffeabSTejas Patel .validate_power_state = versal_validate_power_state, 2405a8ffeabSTejas Patel .get_sys_suspend_power_state = versal_get_sys_suspend_power_state, 241f91c3cb1SSiva Durga Prasad Paladugu }; 242f91c3cb1SSiva Durga Prasad Paladugu 243f91c3cb1SSiva Durga Prasad Paladugu /******************************************************************************* 244f91c3cb1SSiva Durga Prasad Paladugu * Export the platform specific power ops. 245f91c3cb1SSiva Durga Prasad Paladugu ******************************************************************************/ 246f7c48d9eSVenkatesh Yadav Abbarapu int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint, 247f91c3cb1SSiva Durga Prasad Paladugu const struct plat_psci_ops **psci_ops) 248f91c3cb1SSiva Durga Prasad Paladugu { 249f91c3cb1SSiva Durga Prasad Paladugu versal_sec_entry = sec_entrypoint; 250f91c3cb1SSiva Durga Prasad Paladugu 251f91c3cb1SSiva Durga Prasad Paladugu *psci_ops = &versal_nopmc_psci_ops; 252f91c3cb1SSiva Durga Prasad Paladugu 253f91c3cb1SSiva Durga Prasad Paladugu return 0; 254f91c3cb1SSiva Durga Prasad Paladugu } 255