1 /* 2 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef VERSAL_DEF_H 10 #define VERSAL_DEF_H 11 12 #include <plat/arm/common/smccc_def.h> 13 #include <plat/common/common_def.h> 14 15 #define PLATFORM_MASK GENMASK(27U, 24U) 16 #define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 17 18 /* number of interrupt handlers. increase as required */ 19 #define MAX_INTR_EL3 2 20 /* List all consoles */ 21 #define VERSAL_CONSOLE_ID_pl011 1 22 #define VERSAL_CONSOLE_ID_pl011_0 1 23 #define VERSAL_CONSOLE_ID_pl011_1 2 24 #define VERSAL_CONSOLE_ID_dcc 3 25 #define VERSAL_CONSOLE_ID_dtb 4 26 27 #define CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) 28 29 /* Runtime console */ 30 #define RT_CONSOLE_ID_pl011 1 31 #define RT_CONSOLE_ID_pl011_0 1 32 #define RT_CONSOLE_ID_pl011_1 2 33 #define RT_CONSOLE_ID_dcc 3 34 #define RT_CONSOLE_ID_dtb 4 35 36 #define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME) 37 38 /* List of platforms */ 39 #define VERSAL_SILICON U(0) 40 #define VERSAL_SPP U(1) 41 #define VERSAL_EMU U(2) 42 #define VERSAL_QEMU U(3) 43 #define VERSAL_COSIM U(7) 44 45 /* Firmware Image Package */ 46 #define VERSAL_PRIMARY_CPU 0 47 48 /******************************************************************************* 49 * memory map related constants 50 ******************************************************************************/ 51 #define DEVICE0_BASE 0xFF000000 52 #define DEVICE0_SIZE 0x00E00000 53 #define DEVICE1_BASE 0xF9000000 54 #define DEVICE1_SIZE 0x00800000 55 56 /******************************************************************************* 57 * IRQ constants 58 ******************************************************************************/ 59 #define VERSAL_IRQ_SEC_PHY_TIMER U(29) 60 #define ARM_IRQ_SEC_PHY_TIMER 29 61 62 /******************************************************************************* 63 * CCI-400 related constants 64 ******************************************************************************/ 65 #define PLAT_ARM_CCI_BASE 0xFD000000 66 #define PLAT_ARM_CCI_SIZE 0x00100000 67 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 68 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 69 70 /******************************************************************************* 71 * UART related constants 72 ******************************************************************************/ 73 #define VERSAL_UART0_BASE 0xFF000000 74 #define VERSAL_UART1_BASE 0xFF010000 75 76 #if CONSOLE_IS(pl011) || CONSOLE_IS(dtb) 77 # define UART_BASE VERSAL_UART0_BASE 78 # define UART_TYPE CONSOLE_PL011 79 #elif CONSOLE_IS(pl011_1) 80 # define UART_BASE VERSAL_UART1_BASE 81 # define UART_TYPE CONSOLE_PL011 82 #elif CONSOLE_IS(dcc) 83 # define UART_BASE 0x0 84 # define UART_TYPE CONSOLE_DCC 85 #else 86 # error "invalid VERSAL_CONSOLE" 87 #endif 88 89 /* Runtime console */ 90 #if defined(CONSOLE_RUNTIME) 91 #if RT_CONSOLE_IS(pl011) || RT_CONSOLE_IS(dtb) 92 # define RT_UART_BASE VERSAL_UART0_BASE 93 # define RT_UART_TYPE CONSOLE_PL011 94 #elif RT_CONSOLE_IS(pl011_1) 95 # define RT_UART_BASE VERSAL_UART1_BASE 96 # define RT_UART_TYPE CONSOLE_PL011 97 #elif RT_CONSOLE_IS(dcc) 98 # define RT_UART_BASE 0x0 99 # define RT_UART_TYPE CONSOLE_DCC 100 #else 101 # error "invalid CONSOLE_RUNTIME" 102 #endif 103 #endif 104 105 /******************************************************************************* 106 * Platform related constants 107 ******************************************************************************/ 108 #define UART_BAUDRATE 115200 109 110 /* Access control register defines */ 111 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 112 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 113 114 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 115 #define CRF_BASE 0xFD1A0000 116 #define CRF_SIZE 0x00600000 117 118 /* CRF registers and bitfields */ 119 #define CRF_RST_APU (CRF_BASE + 0X00000300) 120 121 #define CRF_RST_APU_ACPU_RESET (1 << 0) 122 #define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) 123 124 /* IOU SCNTRS */ 125 #define IOU_SCNTRS_BASE U(0xFF140000) 126 #define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) 127 128 /* APU registers and bitfields */ 129 #define FPD_APU_BASE 0xFD5C0000U 130 #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U) 131 #define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U) 132 #define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U) 133 #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U) 134 135 #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U 136 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U 137 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U 138 139 /* PMC registers and bitfields */ 140 #define PMC_GLOBAL_BASE 0xF1110000U 141 #define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U) 142 143 #endif /* VERSAL_DEF_H */ 144