1 /* 2 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef VERSAL_DEF_H 10 #define VERSAL_DEF_H 11 12 #include <plat/arm/common/smccc_def.h> 13 #include <plat/common/common_def.h> 14 15 #define PLATFORM_MASK GENMASK(27U, 24U) 16 #define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 17 18 /* number of interrupt handlers. increase as required */ 19 #define MAX_INTR_EL3 2 20 /* List all consoles */ 21 #define VERSAL_CONSOLE_ID_pl011 1 22 #define VERSAL_CONSOLE_ID_pl011_0 1 23 #define VERSAL_CONSOLE_ID_pl011_1 2 24 #define VERSAL_CONSOLE_ID_dcc 3 25 26 #define CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) 27 28 /* Runtime console */ 29 #define RT_CONSOLE_ID_pl011 1 30 #define RT_CONSOLE_ID_pl011_0 1 31 #define RT_CONSOLE_ID_pl011_1 2 32 #define RT_CONSOLE_ID_dcc 3 33 #define RT_CONSOLE_ID_dtb 4 34 35 #define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME) 36 37 /* List of platforms */ 38 #define VERSAL_SILICON U(0) 39 #define VERSAL_SPP U(1) 40 #define VERSAL_EMU U(2) 41 #define VERSAL_QEMU U(3) 42 #define VERSAL_COSIM U(7) 43 44 /* Firmware Image Package */ 45 #define VERSAL_PRIMARY_CPU 0 46 47 /******************************************************************************* 48 * memory map related constants 49 ******************************************************************************/ 50 #define DEVICE0_BASE 0xFF000000 51 #define DEVICE0_SIZE 0x00E00000 52 #define DEVICE1_BASE 0xF9000000 53 #define DEVICE1_SIZE 0x00800000 54 55 /******************************************************************************* 56 * IRQ constants 57 ******************************************************************************/ 58 #define VERSAL_IRQ_SEC_PHY_TIMER U(29) 59 #define ARM_IRQ_SEC_PHY_TIMER 29 60 61 /******************************************************************************* 62 * CCI-400 related constants 63 ******************************************************************************/ 64 #define PLAT_ARM_CCI_BASE 0xFD000000 65 #define PLAT_ARM_CCI_SIZE 0x00100000 66 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 67 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 68 69 /******************************************************************************* 70 * UART related constants 71 ******************************************************************************/ 72 #define VERSAL_UART0_BASE 0xFF000000 73 #define VERSAL_UART1_BASE 0xFF010000 74 75 #if CONSOLE_IS(pl011) 76 # define UART_BASE VERSAL_UART0_BASE 77 # define UART_TYPE CONSOLE_PL011 78 #elif CONSOLE_IS(pl011_1) 79 # define UART_BASE VERSAL_UART1_BASE 80 # define UART_TYPE CONSOLE_PL011 81 #elif CONSOLE_IS(dcc) 82 # define UART_BASE 0x0 83 # define UART_TYPE CONSOLE_DCC 84 #else 85 # error "invalid VERSAL_CONSOLE" 86 #endif 87 88 /* Runtime console */ 89 #if defined(CONSOLE_RUNTIME) 90 #if RT_CONSOLE_IS(pl011) || RT_CONSOLE_IS(dtb) 91 # define RT_UART_BASE VERSAL_UART0_BASE 92 # define RT_UART_TYPE CONSOLE_PL011 93 #elif RT_CONSOLE_IS(pl011_1) 94 # define RT_UART_BASE VERSAL_UART1_BASE 95 # define RT_UART_TYPE CONSOLE_PL011 96 #elif RT_CONSOLE_IS(dcc) 97 # define RT_UART_BASE 0x0 98 # define RT_UART_TYPE CONSOLE_DCC 99 #else 100 # error "invalid CONSOLE_RUNTIME" 101 #endif 102 #endif 103 104 /******************************************************************************* 105 * Platform related constants 106 ******************************************************************************/ 107 #define UART_BAUDRATE 115200 108 109 /* Access control register defines */ 110 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 111 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 112 113 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 114 #define CRF_BASE 0xFD1A0000 115 #define CRF_SIZE 0x00600000 116 117 /* CRF registers and bitfields */ 118 #define CRF_RST_APU (CRF_BASE + 0X00000300) 119 120 #define CRF_RST_APU_ACPU_RESET (1 << 0) 121 #define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) 122 123 /* IOU SCNTRS */ 124 #define IOU_SCNTRS_BASE U(0xFF140000) 125 #define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) 126 127 /* APU registers and bitfields */ 128 #define FPD_APU_BASE 0xFD5C0000U 129 #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U) 130 #define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U) 131 #define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U) 132 #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U) 133 134 #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U 135 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U 136 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U 137 138 /* PMC registers and bitfields */ 139 #define PMC_GLOBAL_BASE 0xF1110000U 140 #define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U) 141 142 #endif /* VERSAL_DEF_H */ 143