1 /* 2 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef VERSAL_DEF_H 8 #define VERSAL_DEF_H 9 10 #include <plat/arm/common/smccc_def.h> 11 #include <plat/common/common_def.h> 12 13 /* List all consoles */ 14 #define VERSAL_CONSOLE_ID_pl011 1 15 #define VERSAL_CONSOLE_ID_pl011_0 1 16 #define VERSAL_CONSOLE_ID_pl011_1 2 17 #define VERSAL_CONSOLE_ID_dcc 3 18 19 #define VERSAL_CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) 20 21 /* List all supported platforms */ 22 #define VERSAL_PLATFORM_ID_versal_virt 1 23 #define VERSAL_PLATFORM_ID_spp_itr6 2 24 #define VERSAL_PLATFORM_ID_emu_itr6 3 25 #define VERSAL_PLATFORM_ID_silicon 4 26 27 #define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM) 28 29 /* Firmware Image Package */ 30 #define VERSAL_PRIMARY_CPU 0 31 32 /******************************************************************************* 33 * memory map related constants 34 ******************************************************************************/ 35 #define DEVICE0_BASE 0xFF000000 36 #define DEVICE0_SIZE 0x00E00000 37 #define DEVICE1_BASE 0xF9000000 38 #define DEVICE1_SIZE 0x00800000 39 40 /******************************************************************************* 41 * IRQ constants 42 ******************************************************************************/ 43 #define VERSAL_IRQ_SEC_PHY_TIMER U(29) 44 45 /******************************************************************************* 46 * CCI-400 related constants 47 ******************************************************************************/ 48 #define PLAT_ARM_CCI_BASE 0xFD000000 49 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 50 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 51 52 /******************************************************************************* 53 * UART related constants 54 ******************************************************************************/ 55 #define VERSAL_UART0_BASE 0xFF000000 56 #define VERSAL_UART1_BASE 0xFF010000 57 58 #if VERSAL_CONSOLE_IS(pl011) || VERSAL_CONSOLE_IS(dcc) 59 # define VERSAL_UART_BASE VERSAL_UART0_BASE 60 #elif VERSAL_CONSOLE_IS(pl011_1) 61 # define VERSAL_UART_BASE VERSAL_UART1_BASE 62 #else 63 # error "invalid VERSAL_CONSOLE" 64 #endif 65 66 #define PLAT_VERSAL_CRASH_UART_BASE VERSAL_UART_BASE 67 #define PLAT_VERSAL_CRASH_UART_CLK_IN_HZ VERSAL_UART_CLOCK 68 #define VERSAL_CONSOLE_BAUDRATE VERSAL_UART_BAUDRATE 69 70 /******************************************************************************* 71 * Platform related constants 72 ******************************************************************************/ 73 #if VERSAL_PLATFORM_IS(versal_virt) 74 # define PLATFORM_NAME "Versal Virt" 75 # define VERSAL_UART_CLOCK 25000000 76 # define VERSAL_UART_BAUDRATE 115200 77 # define VERSAL_CPU_CLOCK 2720000 78 #elif VERSAL_PLATFORM_IS(silicon) 79 # define PLATFORM_NAME "Versal Silicon" 80 # define VERSAL_UART_CLOCK 100000000 81 # define VERSAL_UART_BAUDRATE 115200 82 # define VERSAL_CPU_CLOCK 100000000 83 #elif VERSAL_PLATFORM_IS(spp_itr6) 84 # define PLATFORM_NAME "SPP ITR6" 85 # define VERSAL_UART_CLOCK 25000000 86 # define VERSAL_UART_BAUDRATE 115200 87 # define VERSAL_CPU_CLOCK 2720000 88 #elif VERSAL_PLATFORM_IS(emu_itr6) 89 # define PLATFORM_NAME "EMU ITR6" 90 # define VERSAL_UART_CLOCK 212000 91 # define VERSAL_UART_BAUDRATE 9600 92 # define VERSAL_CPU_CLOCK 212000 93 #endif 94 95 /* Access control register defines */ 96 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 97 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 98 99 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 100 #define CRF_BASE 0xFD1A0000 101 #define CRF_SIZE 0x00600000 102 103 /* CRF registers and bitfields */ 104 #define CRF_RST_APU (CRF_BASE + 0X00000300) 105 106 #define CRF_RST_APU_ACPU_RESET (1 << 0) 107 #define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) 108 109 #define FPD_MAINCCI_BASE 0xFD000000 110 #define FPD_MAINCCI_SIZE 0x00100000 111 112 /* APU registers and bitfields */ 113 #define FPD_APU_BASE 0xFD5C0000U 114 #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U) 115 #define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U) 116 #define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U) 117 #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U) 118 119 #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U 120 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U 121 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U 122 123 /* PMC registers and bitfields */ 124 #define PMC_GLOBAL_BASE 0xF1110000U 125 #define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U) 126 127 /* IPI registers and bitfields */ 128 #define IPI0_REG_BASE U(0xFF330000) 129 #define IPI0_TRIG_BIT (1U << 2U) 130 #define PMC_IPI_TRIG_BIT (1U << 1U) 131 #define IPI1_REG_BASE U(0xFF340000) 132 #define IPI1_TRIG_BIT (1U << 3U) 133 #define IPI2_REG_BASE U(0xFF350000) 134 #define IPI2_TRIG_BIT (1U << 4U) 135 #define IPI3_REG_BASE U(0xFF360000) 136 #define IPI3_TRIG_BIT (1U << 5U) 137 #define IPI4_REG_BASE U(0xFF370000) 138 #define IPI4_TRIG_BIT (1U << 5U) 139 #define IPI5_REG_BASE U(0xFF380000) 140 #define IPI5_TRIG_BIT (1U << 6U) 141 142 #endif /* VERSAL_DEF_H */ 143