1*ab36d097STejas Patel /* 2*ab36d097STejas Patel * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*ab36d097STejas Patel * 4*ab36d097STejas Patel * SPDX-License-Identifier: BSD-3-Clause 5*ab36d097STejas Patel */ 6*ab36d097STejas Patel 7*ab36d097STejas Patel #ifndef VERSAL_DEF_H 8*ab36d097STejas Patel #define VERSAL_DEF_H 9*ab36d097STejas Patel 10*ab36d097STejas Patel #include <plat/common/common_def.h> 11*ab36d097STejas Patel 12*ab36d097STejas Patel /* List all consoles */ 13*ab36d097STejas Patel #define VERSAL_CONSOLE_ID_pl011 1 14*ab36d097STejas Patel #define VERSAL_CONSOLE_ID_pl011_0 1 15*ab36d097STejas Patel #define VERSAL_CONSOLE_ID_pl011_1 2 16*ab36d097STejas Patel #define VERSAL_CONSOLE_ID_dcc 3 17*ab36d097STejas Patel 18*ab36d097STejas Patel #define VERSAL_CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) 19*ab36d097STejas Patel 20*ab36d097STejas Patel /* List all supported platforms */ 21*ab36d097STejas Patel #define VERSAL_PLATFORM_ID_versal_virt 1 22*ab36d097STejas Patel 23*ab36d097STejas Patel #define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM) 24*ab36d097STejas Patel 25*ab36d097STejas Patel /* Firmware Image Package */ 26*ab36d097STejas Patel #define VERSAL_PRIMARY_CPU 0 27*ab36d097STejas Patel 28*ab36d097STejas Patel /******************************************************************************* 29*ab36d097STejas Patel * memory map related constants 30*ab36d097STejas Patel ******************************************************************************/ 31*ab36d097STejas Patel #define DEVICE0_BASE 0xFF000000 32*ab36d097STejas Patel #define DEVICE0_SIZE 0x00E00000 33*ab36d097STejas Patel #define DEVICE1_BASE 0xF9000000 34*ab36d097STejas Patel #define DEVICE1_SIZE 0x00800000 35*ab36d097STejas Patel 36*ab36d097STejas Patel /* CRL */ 37*ab36d097STejas Patel #define VERSAL_CRL 0xFF5E0000 38*ab36d097STejas Patel #define VERSAL_CRL_IOU_SWITCH_CTRL (VERSAL_CRL + 0x114) 39*ab36d097STejas Patel #define VERSAL_CRL_TIMESTAMP_REF_CTRL (VERSAL_CRL + 0x14C) 40*ab36d097STejas Patel #define VERSAL_CRL_RST_TIMESTAMP_OFFSET (VERSAL_CRL + 0x348) 41*ab36d097STejas Patel 42*ab36d097STejas Patel #define VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1 << 25) 43*ab36d097STejas Patel #define VERSAL_IOU_SWITCH_CTRL_CLKACT_BIT (1 << 25) 44*ab36d097STejas Patel #define VERSAL_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 45*ab36d097STejas Patel 46*ab36d097STejas Patel /* IOU SCNTRS */ 47*ab36d097STejas Patel #define VERSAL_IOU_SCNTRS 0xFF140000 48*ab36d097STejas Patel #define VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG (VERSAL_IOU_SCNTRS + 0x0) 49*ab36d097STejas Patel #define VERSAL_IOU_SCNTRS_BASE_FREQ (VERSAL_IOU_SCNTRS + 0x20) 50*ab36d097STejas Patel 51*ab36d097STejas Patel #define VERSAL_IOU_SCNTRS_CONTROL_EN 1 52*ab36d097STejas Patel 53*ab36d097STejas Patel /******************************************************************************* 54*ab36d097STejas Patel * IRQ constants 55*ab36d097STejas Patel ******************************************************************************/ 56*ab36d097STejas Patel #define VERSAL_IRQ_SEC_PHY_TIMER 29 57*ab36d097STejas Patel 58*ab36d097STejas Patel /******************************************************************************* 59*ab36d097STejas Patel * UART related constants 60*ab36d097STejas Patel ******************************************************************************/ 61*ab36d097STejas Patel #define VERSAL_UART0_BASE 0xFF000000 62*ab36d097STejas Patel #define VERSAL_UART1_BASE 0xFF010000 63*ab36d097STejas Patel 64*ab36d097STejas Patel #if VERSAL_CONSOLE_IS(pl011) 65*ab36d097STejas Patel # define VERSAL_UART_BASE VERSAL_UART0_BASE 66*ab36d097STejas Patel #elif VERSAL_CONSOLE_IS(pl011_1) 67*ab36d097STejas Patel # define VERSAL_UART_BASE VERSAL_UART1_BASE 68*ab36d097STejas Patel #else 69*ab36d097STejas Patel # error "invalid VERSAL_CONSOLE" 70*ab36d097STejas Patel #endif 71*ab36d097STejas Patel 72*ab36d097STejas Patel #define PLAT_VERSAL_CRASH_UART_BASE VERSAL_UART_BASE 73*ab36d097STejas Patel #define PLAT_VERSAL_CRASH_UART_CLK_IN_HZ VERSAL_UART_CLOCK 74*ab36d097STejas Patel #define VERSAL_CONSOLE_BAUDRATE VERSAL_UART_BAUDRATE 75*ab36d097STejas Patel 76*ab36d097STejas Patel /******************************************************************************* 77*ab36d097STejas Patel * Platform related constants 78*ab36d097STejas Patel ******************************************************************************/ 79*ab36d097STejas Patel #if VERSAL_PLATFORM_IS(versal_virt) 80*ab36d097STejas Patel # define PLATFORM_NAME "Versal Virt" 81*ab36d097STejas Patel # define VERSAL_UART_CLOCK 25000000 82*ab36d097STejas Patel # define VERSAL_UART_BAUDRATE 115200 83*ab36d097STejas Patel # define VERSAL_CPU_CLOCK 62500000 84*ab36d097STejas Patel #endif 85*ab36d097STejas Patel 86*ab36d097STejas Patel /* Access control register defines */ 87*ab36d097STejas Patel #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 88*ab36d097STejas Patel #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 89*ab36d097STejas Patel 90*ab36d097STejas Patel /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 91*ab36d097STejas Patel #define CRF_BASE 0xFD1A0000 92*ab36d097STejas Patel #define CRF_SIZE 0x00600000 93*ab36d097STejas Patel 94*ab36d097STejas Patel /* CRF registers and bitfields */ 95*ab36d097STejas Patel #define CRF_RST_APU (CRF_BASE + 0X00000300) 96*ab36d097STejas Patel 97*ab36d097STejas Patel #define CRF_RST_APU_ACPU_RESET (1 << 0) 98*ab36d097STejas Patel #define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) 99*ab36d097STejas Patel 100*ab36d097STejas Patel /* APU registers and bitfields */ 101*ab36d097STejas Patel #define FPD_APU_BASE 0xFD5C0000 102*ab36d097STejas Patel #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20) 103*ab36d097STejas Patel #define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40) 104*ab36d097STejas Patel #define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44) 105*ab36d097STejas Patel #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90) 106*ab36d097STejas Patel 107*ab36d097STejas Patel #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8 108*ab36d097STejas Patel 109*ab36d097STejas Patel #endif /* VERSAL_DEF_H */ 110