1ab36d097STejas Patel /* 2619bc13eSMichal Simek * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 3e497421dSTanmay Shah * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 4079c6e24SAkshay Belsare * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5ab36d097STejas Patel * 6ab36d097STejas Patel * SPDX-License-Identifier: BSD-3-Clause 7ab36d097STejas Patel */ 8ab36d097STejas Patel 9ab36d097STejas Patel #ifndef VERSAL_DEF_H 10ab36d097STejas Patel #define VERSAL_DEF_H 11ab36d097STejas Patel 1253adebadSManish V Badarkhe #include <plat/arm/common/smccc_def.h> 13ab36d097STejas Patel #include <plat/common/common_def.h> 14ab36d097STejas Patel 15079c6e24SAkshay Belsare #define PLATFORM_MASK GENMASK(27U, 24U) 16079c6e24SAkshay Belsare #define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 17079c6e24SAkshay Belsare 18e497421dSTanmay Shah /* number of interrupt handlers. increase as required */ 19e497421dSTanmay Shah #define MAX_INTR_EL3 2 20ab36d097STejas Patel /* List all consoles */ 21ab36d097STejas Patel #define VERSAL_CONSOLE_ID_pl011 1 22ab36d097STejas Patel #define VERSAL_CONSOLE_ID_pl011_0 1 23ab36d097STejas Patel #define VERSAL_CONSOLE_ID_pl011_1 2 24ab36d097STejas Patel #define VERSAL_CONSOLE_ID_dcc 3 25ab36d097STejas Patel 2604a48335SMichal Simek #define CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) 27ab36d097STejas Patel 28ab36d097STejas Patel /* List all supported platforms */ 29ab36d097STejas Patel #define VERSAL_PLATFORM_ID_versal_virt 1 30be73459aSVenkatesh Yadav Abbarapu #define VERSAL_PLATFORM_ID_spp_itr6 2 31be73459aSVenkatesh Yadav Abbarapu #define VERSAL_PLATFORM_ID_emu_itr6 3 32d69bbd0eSSiva Durga Prasad Paladugu #define VERSAL_PLATFORM_ID_silicon 4 33ab36d097STejas Patel 34ab36d097STejas Patel #define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM) 35ab36d097STejas Patel 36ab36d097STejas Patel /* Firmware Image Package */ 37ab36d097STejas Patel #define VERSAL_PRIMARY_CPU 0 38ab36d097STejas Patel 39ab36d097STejas Patel /******************************************************************************* 40ab36d097STejas Patel * memory map related constants 41ab36d097STejas Patel ******************************************************************************/ 42ab36d097STejas Patel #define DEVICE0_BASE 0xFF000000 43ab36d097STejas Patel #define DEVICE0_SIZE 0x00E00000 44ab36d097STejas Patel #define DEVICE1_BASE 0xF9000000 45ab36d097STejas Patel #define DEVICE1_SIZE 0x00800000 46ab36d097STejas Patel 47ab36d097STejas Patel /******************************************************************************* 48ab36d097STejas Patel * IRQ constants 49ab36d097STejas Patel ******************************************************************************/ 50b2bb3efbSAbhyuday Godhasara #define VERSAL_IRQ_SEC_PHY_TIMER U(29) 51*7ff4d4fbSPrasad Kummari #define ARM_IRQ_SEC_PHY_TIMER 29 52ab36d097STejas Patel 53ab36d097STejas Patel /******************************************************************************* 545a8ffeabSTejas Patel * CCI-400 related constants 555a8ffeabSTejas Patel ******************************************************************************/ 565a8ffeabSTejas Patel #define PLAT_ARM_CCI_BASE 0xFD000000 57245d30efSMichal Simek #define PLAT_ARM_CCI_SIZE 0x00100000 585a8ffeabSTejas Patel #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 595a8ffeabSTejas Patel #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 605a8ffeabSTejas Patel 615a8ffeabSTejas Patel /******************************************************************************* 62ab36d097STejas Patel * UART related constants 63ab36d097STejas Patel ******************************************************************************/ 64ab36d097STejas Patel #define VERSAL_UART0_BASE 0xFF000000 65ab36d097STejas Patel #define VERSAL_UART1_BASE 0xFF010000 66ab36d097STejas Patel 6704a48335SMichal Simek #if CONSOLE_IS(pl011) || CONSOLE_IS(dcc) 6804a48335SMichal Simek # define UART_BASE VERSAL_UART0_BASE 6904a48335SMichal Simek #elif CONSOLE_IS(pl011_1) 7004a48335SMichal Simek # define UART_BASE VERSAL_UART1_BASE 71ab36d097STejas Patel #else 72ab36d097STejas Patel # error "invalid VERSAL_CONSOLE" 73ab36d097STejas Patel #endif 74ab36d097STejas Patel 75ab36d097STejas Patel /******************************************************************************* 76ab36d097STejas Patel * Platform related constants 77ab36d097STejas Patel ******************************************************************************/ 78ab36d097STejas Patel #if VERSAL_PLATFORM_IS(versal_virt) 79ab36d097STejas Patel # define PLATFORM_NAME "Versal Virt" 8004a48335SMichal Simek # define UART_CLOCK 25000000 8104a48335SMichal Simek # define UART_BAUDRATE 115200 82c959c479SSiva Durga Prasad Paladugu # define VERSAL_CPU_CLOCK 2720000 83d69bbd0eSSiva Durga Prasad Paladugu #elif VERSAL_PLATFORM_IS(silicon) 84d69bbd0eSSiva Durga Prasad Paladugu # define PLATFORM_NAME "Versal Silicon" 8504a48335SMichal Simek # define UART_CLOCK 100000000 8604a48335SMichal Simek # define UART_BAUDRATE 115200 87d69bbd0eSSiva Durga Prasad Paladugu # define VERSAL_CPU_CLOCK 100000000 88be73459aSVenkatesh Yadav Abbarapu #elif VERSAL_PLATFORM_IS(spp_itr6) 89be73459aSVenkatesh Yadav Abbarapu # define PLATFORM_NAME "SPP ITR6" 9004a48335SMichal Simek # define UART_CLOCK 25000000 9104a48335SMichal Simek # define UART_BAUDRATE 115200 92be73459aSVenkatesh Yadav Abbarapu # define VERSAL_CPU_CLOCK 2720000 93be73459aSVenkatesh Yadav Abbarapu #elif VERSAL_PLATFORM_IS(emu_itr6) 94be73459aSVenkatesh Yadav Abbarapu # define PLATFORM_NAME "EMU ITR6" 9504a48335SMichal Simek # define UART_CLOCK 212000 9604a48335SMichal Simek # define UART_BAUDRATE 9600 97be73459aSVenkatesh Yadav Abbarapu # define VERSAL_CPU_CLOCK 212000 98ab36d097STejas Patel #endif 99ab36d097STejas Patel 100ab36d097STejas Patel /* Access control register defines */ 101ab36d097STejas Patel #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 102ab36d097STejas Patel #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 103ab36d097STejas Patel 104ab36d097STejas Patel /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 105ab36d097STejas Patel #define CRF_BASE 0xFD1A0000 106ab36d097STejas Patel #define CRF_SIZE 0x00600000 107ab36d097STejas Patel 108ab36d097STejas Patel /* CRF registers and bitfields */ 109ab36d097STejas Patel #define CRF_RST_APU (CRF_BASE + 0X00000300) 110ab36d097STejas Patel 111ab36d097STejas Patel #define CRF_RST_APU_ACPU_RESET (1 << 0) 112ab36d097STejas Patel #define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) 113ab36d097STejas Patel 114ab36d097STejas Patel /* APU registers and bitfields */ 1155d1c211eSAbhyuday Godhasara #define FPD_APU_BASE 0xFD5C0000U 1165d1c211eSAbhyuday Godhasara #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U) 1175d1c211eSAbhyuday Godhasara #define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U) 1185d1c211eSAbhyuday Godhasara #define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U) 1195d1c211eSAbhyuday Godhasara #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U) 120ab36d097STejas Patel 1215d1c211eSAbhyuday Godhasara #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U 1225d1c211eSAbhyuday Godhasara #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U 1235d1c211eSAbhyuday Godhasara #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U 124ab36d097STejas Patel 12531ce893eSVenkatesh Yadav Abbarapu /* PMC registers and bitfields */ 1265d1c211eSAbhyuday Godhasara #define PMC_GLOBAL_BASE 0xF1110000U 1275d1c211eSAbhyuday Godhasara #define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U) 12831ce893eSVenkatesh Yadav Abbarapu 129ab36d097STejas Patel #endif /* VERSAL_DEF_H */ 130