1ab36d097STejas Patel /* 2619bc13eSMichal Simek * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 3e497421dSTanmay Shah * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 4*09ac1ca2SMaheedhar Bollapalli * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5ab36d097STejas Patel * 6ab36d097STejas Patel * SPDX-License-Identifier: BSD-3-Clause 7ab36d097STejas Patel */ 8ab36d097STejas Patel 9ab36d097STejas Patel #ifndef VERSAL_DEF_H 10ab36d097STejas Patel #define VERSAL_DEF_H 11ab36d097STejas Patel 1253adebadSManish V Badarkhe #include <plat/arm/common/smccc_def.h> 13ab36d097STejas Patel #include <plat/common/common_def.h> 14ab36d097STejas Patel 15079c6e24SAkshay Belsare #define PLATFORM_MASK GENMASK(27U, 24U) 16079c6e24SAkshay Belsare #define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 17079c6e24SAkshay Belsare 18e497421dSTanmay Shah /* number of interrupt handlers. increase as required */ 19e497421dSTanmay Shah #define MAX_INTR_EL3 2 20ab36d097STejas Patel /* List all consoles */ 21ab36d097STejas Patel #define VERSAL_CONSOLE_ID_pl011 1 22ab36d097STejas Patel #define VERSAL_CONSOLE_ID_pl011_0 1 23ab36d097STejas Patel #define VERSAL_CONSOLE_ID_pl011_1 2 24ab36d097STejas Patel #define VERSAL_CONSOLE_ID_dcc 3 25ab36d097STejas Patel 2604a48335SMichal Simek #define CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) 27ab36d097STejas Patel 28*09ac1ca2SMaheedhar Bollapalli /* List of platforms */ 29*09ac1ca2SMaheedhar Bollapalli #define VERSAL_SILICON U(0) 30*09ac1ca2SMaheedhar Bollapalli #define VERSAL_SPP U(1) 31*09ac1ca2SMaheedhar Bollapalli #define VERSAL_EMU U(2) 32*09ac1ca2SMaheedhar Bollapalli #define VERSAL_QEMU U(3) 33ab36d097STejas Patel 34ab36d097STejas Patel /* Firmware Image Package */ 35ab36d097STejas Patel #define VERSAL_PRIMARY_CPU 0 36ab36d097STejas Patel 37ab36d097STejas Patel /******************************************************************************* 38ab36d097STejas Patel * memory map related constants 39ab36d097STejas Patel ******************************************************************************/ 40ab36d097STejas Patel #define DEVICE0_BASE 0xFF000000 41ab36d097STejas Patel #define DEVICE0_SIZE 0x00E00000 42ab36d097STejas Patel #define DEVICE1_BASE 0xF9000000 43ab36d097STejas Patel #define DEVICE1_SIZE 0x00800000 44ab36d097STejas Patel 45ab36d097STejas Patel /******************************************************************************* 46ab36d097STejas Patel * IRQ constants 47ab36d097STejas Patel ******************************************************************************/ 48b2bb3efbSAbhyuday Godhasara #define VERSAL_IRQ_SEC_PHY_TIMER U(29) 497ff4d4fbSPrasad Kummari #define ARM_IRQ_SEC_PHY_TIMER 29 50ab36d097STejas Patel 51ab36d097STejas Patel /******************************************************************************* 525a8ffeabSTejas Patel * CCI-400 related constants 535a8ffeabSTejas Patel ******************************************************************************/ 545a8ffeabSTejas Patel #define PLAT_ARM_CCI_BASE 0xFD000000 55245d30efSMichal Simek #define PLAT_ARM_CCI_SIZE 0x00100000 565a8ffeabSTejas Patel #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 575a8ffeabSTejas Patel #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 585a8ffeabSTejas Patel 595a8ffeabSTejas Patel /******************************************************************************* 60ab36d097STejas Patel * UART related constants 61ab36d097STejas Patel ******************************************************************************/ 62ab36d097STejas Patel #define VERSAL_UART0_BASE 0xFF000000 63ab36d097STejas Patel #define VERSAL_UART1_BASE 0xFF010000 64ab36d097STejas Patel 6504a48335SMichal Simek #if CONSOLE_IS(pl011) || CONSOLE_IS(dcc) 6604a48335SMichal Simek # define UART_BASE VERSAL_UART0_BASE 6704a48335SMichal Simek #elif CONSOLE_IS(pl011_1) 6804a48335SMichal Simek # define UART_BASE VERSAL_UART1_BASE 69ab36d097STejas Patel #else 70ab36d097STejas Patel # error "invalid VERSAL_CONSOLE" 71ab36d097STejas Patel #endif 72ab36d097STejas Patel 73ab36d097STejas Patel /******************************************************************************* 74ab36d097STejas Patel * Platform related constants 75ab36d097STejas Patel ******************************************************************************/ 7604a48335SMichal Simek #define UART_BAUDRATE 115200 77ab36d097STejas Patel 78ab36d097STejas Patel /* Access control register defines */ 79ab36d097STejas Patel #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 80ab36d097STejas Patel #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 81ab36d097STejas Patel 82ab36d097STejas Patel /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 83ab36d097STejas Patel #define CRF_BASE 0xFD1A0000 84ab36d097STejas Patel #define CRF_SIZE 0x00600000 85ab36d097STejas Patel 86ab36d097STejas Patel /* CRF registers and bitfields */ 87ab36d097STejas Patel #define CRF_RST_APU (CRF_BASE + 0X00000300) 88ab36d097STejas Patel 89ab36d097STejas Patel #define CRF_RST_APU_ACPU_RESET (1 << 0) 90ab36d097STejas Patel #define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) 91ab36d097STejas Patel 92f000744eSPrasad Kummari /* IOU SCNTRS */ 93f000744eSPrasad Kummari #define IOU_SCNTRS_BASE U(0xFF140000) 94f000744eSPrasad Kummari #define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) 95f000744eSPrasad Kummari 96ab36d097STejas Patel /* APU registers and bitfields */ 975d1c211eSAbhyuday Godhasara #define FPD_APU_BASE 0xFD5C0000U 985d1c211eSAbhyuday Godhasara #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U) 995d1c211eSAbhyuday Godhasara #define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U) 1005d1c211eSAbhyuday Godhasara #define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U) 1015d1c211eSAbhyuday Godhasara #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U) 102ab36d097STejas Patel 1035d1c211eSAbhyuday Godhasara #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U 1045d1c211eSAbhyuday Godhasara #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U 1055d1c211eSAbhyuday Godhasara #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U 106ab36d097STejas Patel 10731ce893eSVenkatesh Yadav Abbarapu /* PMC registers and bitfields */ 1085d1c211eSAbhyuday Godhasara #define PMC_GLOBAL_BASE 0xF1110000U 1095d1c211eSAbhyuday Godhasara #define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U) 11031ce893eSVenkatesh Yadav Abbarapu 111ab36d097STejas Patel #endif /* VERSAL_DEF_H */ 112