1 /* 2 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #include <arch.h> 12 #include "versal_def.h" 13 14 /******************************************************************************* 15 * Generic platform constants 16 ******************************************************************************/ 17 18 /* Size of cacheable stacks */ 19 #define PLATFORM_STACK_SIZE U(0x440) 20 21 #define PLATFORM_CORE_COUNT U(2) 22 #define PLAT_MAX_PWR_LVL U(1) 23 #define PLAT_MAX_RET_STATE U(1) 24 #define PLAT_MAX_OFF_STATE U(2) 25 26 /******************************************************************************* 27 * BL31 specific defines. 28 ******************************************************************************/ 29 /* 30 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 31 * present). BL31_BASE is calculated using the current BL31 debug size plus a 32 * little space for growth. 33 */ 34 #ifndef VERSAL_ATF_MEM_BASE 35 # define BL31_BASE U(0xfffe0000) 36 # define BL31_LIMIT U(0x100000000) 37 #else 38 # define BL31_BASE (VERSAL_ATF_MEM_BASE) 39 # define BL31_LIMIT (VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_SIZE) 40 # ifdef VERSAL_ATF_MEM_PROGBITS_SIZE 41 # define BL31_PROGBITS_LIMIT (VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_PROGBITS_SIZE) 42 # endif 43 #endif 44 45 /******************************************************************************* 46 * BL32 specific defines. 47 ******************************************************************************/ 48 #ifndef VERSAL_BL32_MEM_BASE 49 # define BL32_BASE U(0x60000000) 50 # define BL32_LIMIT U(0x80000000) 51 #else 52 # define BL32_BASE (VERSAL_BL32_MEM_BASE) 53 # define BL32_LIMIT (VERSAL_BL32_MEM_BASE + VERSAL_BL32_MEM_SIZE) 54 #endif 55 56 /******************************************************************************* 57 * BL33 specific defines. 58 ******************************************************************************/ 59 #ifndef PRELOADED_BL33_BASE 60 # define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) 61 #else 62 # define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE 63 #endif 64 65 /******************************************************************************* 66 * TSP specific defines. 67 ******************************************************************************/ 68 #define TSP_SEC_MEM_BASE BL32_BASE 69 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) 70 71 /* ID of the secure physical generic timer interrupt used by the TSP */ 72 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 73 74 /******************************************************************************* 75 * Platform specific page table and MMU setup constants 76 ******************************************************************************/ 77 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 78 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 79 #define MAX_MMAP_REGIONS 8 80 #define MAX_XLAT_TABLES 5 81 82 #define CACHE_WRITEBACK_SHIFT 6 83 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 84 85 #define PLAT_GICD_BASE_VALUE U(0xF9000000) 86 #define PLAT_GICR_BASE_VALUE U(0xF9080000) 87 88 /* 89 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 90 * terminology. On a GICv2 system or mode, the lists will be merged and treated 91 * as Group 0 interrupts. 92 */ 93 #define PLAT_VERSAL_G1S_IRQS VERSAL_IRQ_SEC_PHY_TIMER 94 #define PLAT_VERSAL_G0_IRQS VERSAL_IRQ_SEC_PHY_TIMER 95 #define PLAT_VERSAL_IPI_IRQ U(62) 96 97 #define PLAT_VERSAL_G1S_IRQ_PROPS(grp) \ 98 INTR_PROP_DESC(VERSAL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 99 GIC_INTR_CFG_LEVEL) 100 101 #define PLAT_VERSAL_G0_IRQ_PROPS(grp) \ 102 INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \ 103 GIC_INTR_CFG_EDGE), \ 104 105 #define IRQ_MAX 142U 106 107 #endif /* PLATFORM_DEF_H */ 108