1d4821739STejas Patel /* 2d4821739STejas Patel * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*e497421dSTanmay Shah * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4*e497421dSTanmay Shah * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. 5d4821739STejas Patel * 6d4821739STejas Patel * SPDX-License-Identifier: BSD-3-Clause 7d4821739STejas Patel */ 8d4821739STejas Patel 9d4821739STejas Patel #ifndef PLAT_PRIVATE_H 10d4821739STejas Patel #define PLAT_PRIVATE_H 11d4821739STejas Patel 12d4821739STejas Patel #include <lib/xlat_tables/xlat_tables.h> 138b48bfb8SShubhrajyoti Datta #include <bl31/interrupt_mgmt.h> 14d4821739STejas Patel 15*e497421dSTanmay Shah typedef struct versal_intr_info_type_el3 { 16*e497421dSTanmay Shah uint32_t id; 17*e497421dSTanmay Shah interrupt_type_handler_t handler; 18*e497421dSTanmay Shah } versal_intr_info_type_el3_t; 19*e497421dSTanmay Shah 20d4821739STejas Patel void versal_config_setup(void); 21d4821739STejas Patel 22d4821739STejas Patel const mmap_region_t *plat_versal_get_mmap(void); 23d4821739STejas Patel 24d4821739STejas Patel void plat_versal_gic_driver_init(void); 25d4821739STejas Patel void plat_versal_gic_init(void); 26d4821739STejas Patel void plat_versal_gic_cpuif_enable(void); 27d4821739STejas Patel void plat_versal_gic_cpuif_disable(void); 28d4821739STejas Patel void plat_versal_gic_pcpu_init(void); 295a8ffeabSTejas Patel void plat_versal_gic_save(void); 305a8ffeabSTejas Patel void plat_versal_gic_resume(void); 31d4821739STejas Patel 32912b7a6fSVenkatesh Yadav Abbarapu uint32_t versal_calc_core_pos(u_register_t mpidr); 338b48bfb8SShubhrajyoti Datta /* 348b48bfb8SShubhrajyoti Datta * Register handler to specific GIC entrance 358b48bfb8SShubhrajyoti Datta * for INTR_TYPE_EL3 type of interrupt 368b48bfb8SShubhrajyoti Datta */ 37912b7a6fSVenkatesh Yadav Abbarapu int32_t request_intr_type_el3(uint32_t irq, interrupt_type_handler_t fiq_handler); 38d4821739STejas Patel 39d4821739STejas Patel #endif /* PLAT_PRIVATE_H */ 40