xref: /rk3399_ARM-atf/plat/xilinx/versal/include/plat_macros.S (revision 09d40e0e08283a249e7dce0e106c07c5141f9b7e)
1f91c3cb1SSiva Durga Prasad Paladugu/*
2f91c3cb1SSiva Durga Prasad Paladugu * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3f91c3cb1SSiva Durga Prasad Paladugu *
4f91c3cb1SSiva Durga Prasad Paladugu * SPDX-License-Identifier: BSD-3-Clause
5f91c3cb1SSiva Durga Prasad Paladugu */
6f91c3cb1SSiva Durga Prasad Paladugu
7f91c3cb1SSiva Durga Prasad Paladugu#ifndef PLAT_MACROS_S
8f91c3cb1SSiva Durga Prasad Paladugu#define PLAT_MACROS_S
9f91c3cb1SSiva Durga Prasad Paladugu
10*09d40e0eSAntonio Nino Diaz#include <drivers/arm/gic_common.h>
11*09d40e0eSAntonio Nino Diaz#include <drivers/arm/gicv2.h>
12*09d40e0eSAntonio Nino Diaz#include <drivers/arm/gicv3.h>
13*09d40e0eSAntonio Nino Diaz
14f91c3cb1SSiva Durga Prasad Paladugu#include "../include/platform_def.h"
15f91c3cb1SSiva Durga Prasad Paladugu
16f91c3cb1SSiva Durga Prasad Paladugu.section .rodata.gic_reg_name, "aS"
17f91c3cb1SSiva Durga Prasad Paladugu/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */
18f91c3cb1SSiva Durga Prasad Paladugugicc_regs:
19f91c3cb1SSiva Durga Prasad Paladugu	.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
20f91c3cb1SSiva Durga Prasad Paladugu
21f91c3cb1SSiva Durga Prasad Paladugu/* Applicable only to GICv3 with SRE enabled */
22f91c3cb1SSiva Durga Prasad Paladuguicc_regs:
23f91c3cb1SSiva Durga Prasad Paladugu	.asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", ""
24f91c3cb1SSiva Durga Prasad Paladugu
25f91c3cb1SSiva Durga Prasad Paladugu/* Registers common to both GICv2 and GICv3 */
26f91c3cb1SSiva Durga Prasad Paladugugicd_pend_reg:
27f91c3cb1SSiva Durga Prasad Paladugu	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
28f91c3cb1SSiva Durga Prasad Paladugunewline:
29f91c3cb1SSiva Durga Prasad Paladugu	.asciz "\n"
30f91c3cb1SSiva Durga Prasad Paladuguspacer:
31f91c3cb1SSiva Durga Prasad Paladugu	.asciz ":\t\t0x"
32f91c3cb1SSiva Durga Prasad Paladugu
33f91c3cb1SSiva Durga Prasad Paladugu	/* ---------------------------------------------
34f91c3cb1SSiva Durga Prasad Paladugu	 * The below utility macro prints out relevant GIC
35f91c3cb1SSiva Durga Prasad Paladugu	 * registers whenever an unhandled exception is
36f91c3cb1SSiva Durga Prasad Paladugu	 * taken in BL31 on Versal platform.
37f91c3cb1SSiva Durga Prasad Paladugu	 * Expects: GICD base in x16, GICC base in x17
38f91c3cb1SSiva Durga Prasad Paladugu	 * Clobbers: x0 - x10, sp
39f91c3cb1SSiva Durga Prasad Paladugu	 * ---------------------------------------------
40f91c3cb1SSiva Durga Prasad Paladugu	 */
41f91c3cb1SSiva Durga Prasad Paladugu	.macro versal_print_gic_regs
42f91c3cb1SSiva Durga Prasad Paladugu	/* Check for GICv3 system register access */
43f91c3cb1SSiva Durga Prasad Paladugu	mrs	x7, id_aa64pfr0_el1
44f91c3cb1SSiva Durga Prasad Paladugu	ubfx	x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
45f91c3cb1SSiva Durga Prasad Paladugu	cmp	x7, #1
46f91c3cb1SSiva Durga Prasad Paladugu	b.ne	print_gicv2
47f91c3cb1SSiva Durga Prasad Paladugu
48f91c3cb1SSiva Durga Prasad Paladugu	/* Check for SRE enable */
49f91c3cb1SSiva Durga Prasad Paladugu	mrs	x8, ICC_SRE_EL3
50f91c3cb1SSiva Durga Prasad Paladugu	tst	x8, #ICC_SRE_SRE_BIT
51f91c3cb1SSiva Durga Prasad Paladugu	b.eq	print_gicv2
52f91c3cb1SSiva Durga Prasad Paladugu
53f91c3cb1SSiva Durga Prasad Paladugu	/* Load the icc reg list to x6 */
54f91c3cb1SSiva Durga Prasad Paladugu	adr	x6, icc_regs
55f91c3cb1SSiva Durga Prasad Paladugu	/* Load the icc regs to gp regs used by str_in_crash_buf_print */
56f91c3cb1SSiva Durga Prasad Paladugu	mrs	x8, ICC_HPPIR0_EL1
57f91c3cb1SSiva Durga Prasad Paladugu	mrs	x9, ICC_HPPIR1_EL1
58f91c3cb1SSiva Durga Prasad Paladugu	mrs	x10, ICC_CTLR_EL3
59f91c3cb1SSiva Durga Prasad Paladugu	/* Store to the crash buf and print to console */
60f91c3cb1SSiva Durga Prasad Paladugu	bl	str_in_crash_buf_print
61f91c3cb1SSiva Durga Prasad Paladugu	b	print_gic_common
62f91c3cb1SSiva Durga Prasad Paladugu
63f91c3cb1SSiva Durga Prasad Paladuguprint_gicv2:
64f91c3cb1SSiva Durga Prasad Paladugu	/* Load the gicc reg list to x6 */
65f91c3cb1SSiva Durga Prasad Paladugu	adr	x6, gicc_regs
66f91c3cb1SSiva Durga Prasad Paladugu	/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
67f91c3cb1SSiva Durga Prasad Paladugu	ldr	w8, [x17, #GICC_HPPIR]
68f91c3cb1SSiva Durga Prasad Paladugu	ldr	w9, [x17, #GICC_AHPPIR]
69f91c3cb1SSiva Durga Prasad Paladugu	ldr	w10, [x17, #GICC_CTLR]
70f91c3cb1SSiva Durga Prasad Paladugu	/* Store to the crash buf and print to console */
71f91c3cb1SSiva Durga Prasad Paladugu	bl	str_in_crash_buf_print
72f91c3cb1SSiva Durga Prasad Paladugu
73f91c3cb1SSiva Durga Prasad Paladuguprint_gic_common:
74f91c3cb1SSiva Durga Prasad Paladugu	/* Print the GICD_ISPENDR regs */
75f91c3cb1SSiva Durga Prasad Paladugu	add	x7, x16, #GICD_ISPENDR
76f91c3cb1SSiva Durga Prasad Paladugu	adr	x4, gicd_pend_reg
77f91c3cb1SSiva Durga Prasad Paladugu	bl	asm_print_str
78f91c3cb1SSiva Durga Prasad Paladugugicd_ispendr_loop:
79f91c3cb1SSiva Durga Prasad Paladugu	sub	x4, x7, x16
80f91c3cb1SSiva Durga Prasad Paladugu	cmp	x4, #0x280
81f91c3cb1SSiva Durga Prasad Paladugu	b.eq	exit_print_gic_regs
82f91c3cb1SSiva Durga Prasad Paladugu	bl	asm_print_hex
83f91c3cb1SSiva Durga Prasad Paladugu
84f91c3cb1SSiva Durga Prasad Paladugu	adr	x4, spacer
85f91c3cb1SSiva Durga Prasad Paladugu	bl	asm_print_str
86f91c3cb1SSiva Durga Prasad Paladugu
87f91c3cb1SSiva Durga Prasad Paladugu	ldr	x4, [x7], #8
88f91c3cb1SSiva Durga Prasad Paladugu	bl	asm_print_hex
89f91c3cb1SSiva Durga Prasad Paladugu
90f91c3cb1SSiva Durga Prasad Paladugu	adr	x4, newline
91f91c3cb1SSiva Durga Prasad Paladugu	bl	asm_print_str
92f91c3cb1SSiva Durga Prasad Paladugu	b	gicd_ispendr_loop
93f91c3cb1SSiva Durga Prasad Paladuguexit_print_gic_regs:
94f91c3cb1SSiva Durga Prasad Paladugu	.endm
95f91c3cb1SSiva Durga Prasad Paladugu
96f91c3cb1SSiva Durga Prasad Paladugu	/* ---------------------------------------------
97f91c3cb1SSiva Durga Prasad Paladugu	 * The below required platform porting macro
98f91c3cb1SSiva Durga Prasad Paladugu	 * prints out relevant GIC and CCI registers
99f91c3cb1SSiva Durga Prasad Paladugu	 * whenever an unhandled exception is taken in
100f91c3cb1SSiva Durga Prasad Paladugu	 * BL31.
101f91c3cb1SSiva Durga Prasad Paladugu	 * Clobbers: x0 - x10, x16, x17, sp
102f91c3cb1SSiva Durga Prasad Paladugu	 * ---------------------------------------------
103f91c3cb1SSiva Durga Prasad Paladugu	 */
104f91c3cb1SSiva Durga Prasad Paladugu	.macro plat_crash_print_regs
105f91c3cb1SSiva Durga Prasad Paladugu	mov_imm	x17, PLAT_VERSAL_GICD_BASE
106f91c3cb1SSiva Durga Prasad Paladugu	mov_imm	x16, PLAT_VERSAL_GICR_BASE
107f91c3cb1SSiva Durga Prasad Paladugu	versal_print_gic_regs
108f91c3cb1SSiva Durga Prasad Paladugu	.endm
109f91c3cb1SSiva Durga Prasad Paladugu
110f91c3cb1SSiva Durga Prasad Paladugu#endif /* PLAT_MACROS_S */
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