1 /* 2 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 #include <plat_arm.h> 12 #include <plat_private.h> 13 #include <bl31/bl31.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <drivers/arm/dcc.h> 17 #include <drivers/arm/pl011.h> 18 #include <drivers/console.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables_v2.h> 21 #include <plat/common/platform.h> 22 #include <versal_def.h> 23 #include <plat_private.h> 24 #include <plat_startup.h> 25 #include <pm_ipi.h> 26 #include "pm_client.h" 27 #include "pm_api_sys.h" 28 29 static entry_point_info_t bl32_image_ep_info; 30 static entry_point_info_t bl33_image_ep_info; 31 32 /* 33 * Return a pointer to the 'entry_point_info' structure of the next image for 34 * the security state specified. BL33 corresponds to the non-secure image type 35 * while BL32 corresponds to the secure image type. A NULL pointer is returned 36 * if the image does not exist. 37 */ 38 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 39 { 40 assert(sec_state_is_valid(type)); 41 42 if (type == NON_SECURE) { 43 return &bl33_image_ep_info; 44 } 45 46 return &bl32_image_ep_info; 47 } 48 49 /* 50 * Set the build time defaults,if we can't find any config data. 51 */ 52 static inline void bl31_set_default_config(void) 53 { 54 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE; 55 bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr_for_bl32_entry(); 56 bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint(); 57 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 58 DISABLE_ALL_EXCEPTIONS); 59 } 60 61 /* 62 * Perform any BL31 specific platform actions. Here is an opportunity to copy 63 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 64 * are lost (potentially). This needs to be done before the MMU is initialized 65 * so that the memory layout can be used while creating page tables. 66 */ 67 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 68 u_register_t arg2, u_register_t arg3) 69 { 70 uint64_t atf_handoff_addr; 71 uint32_t payload[PAYLOAD_ARG_CNT], max_size = ATF_HANDOFF_PARAMS_MAX_SIZE; 72 enum pm_ret_status ret_status; 73 uint64_t addr[ATF_HANDOFF_PARAMS_MAX_SIZE]; 74 75 if (VERSAL_CONSOLE_IS(pl011) || (VERSAL_CONSOLE_IS(pl011_1))) { 76 static console_t versal_runtime_console; 77 /* Initialize the console to provide early debug support */ 78 int32_t rc = console_pl011_register((uintptr_t)VERSAL_UART_BASE, 79 (uint32_t)VERSAL_UART_CLOCK, 80 (uint32_t)VERSAL_UART_BAUDRATE, 81 &versal_runtime_console); 82 if (rc == 0) { 83 panic(); 84 } 85 86 console_set_scope(&versal_runtime_console, (uint32_t)(CONSOLE_FLAG_BOOT | 87 CONSOLE_FLAG_RUNTIME)); 88 } else if (VERSAL_CONSOLE_IS(dcc)) { 89 /* Initialize the dcc console for debug */ 90 int32_t rc = console_dcc_register(); 91 if (rc == 0) { 92 panic(); 93 } 94 } else { 95 NOTICE("BL31: Did not register for any console.\n"); 96 } 97 98 /* Initialize the platform config for future decision making */ 99 versal_config_setup(); 100 101 /* 102 * Do initial security configuration to allow DRAM/device access. On 103 * Base VERSAL only DRAM security is programmable (via TrustZone), but 104 * other platforms might have more programmable security devices 105 * present. 106 */ 107 108 /* Populate common information for BL32 and BL33 */ 109 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 110 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 111 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 112 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 113 114 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS, 115 (uintptr_t)addr >> 32U, (uintptr_t)addr, max_size); 116 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); 117 if (ret_status == PM_RET_SUCCESS) { 118 INFO("BL31: GET_HANDOFF_PARAMS call success=%d\n", ret_status); 119 atf_handoff_addr = (uintptr_t)&addr; 120 } else { 121 ERROR("BL31: GET_HANDOFF_PARAMS Failed, read atf_handoff_addr from reg\n"); 122 atf_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4); 123 } 124 125 enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info, 126 &bl33_image_ep_info, 127 atf_handoff_addr); 128 if (ret == FSBL_HANDOFF_NO_STRUCT || ret == FSBL_HANDOFF_INVAL_STRUCT) { 129 bl31_set_default_config(); 130 } else if (ret == FSBL_HANDOFF_TOO_MANY_PARTS) { 131 ERROR("BL31: Error too many partitions %u\n", ret); 132 } else if (ret != FSBL_HANDOFF_SUCCESS) { 133 panic(); 134 } else { 135 INFO("BL31: PLM to TF-A handover success %u\n", ret); 136 } 137 138 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 139 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 140 } 141 142 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 143 144 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 145 { 146 static uint32_t index; 147 uint32_t i; 148 149 /* Validate 'handler' and 'id' parameters */ 150 if (handler == NULL || index >= MAX_INTR_EL3) { 151 return -EINVAL; 152 } 153 154 /* Check if a handler has already been registered */ 155 for (i = 0; i < index; i++) { 156 if (id == type_el3_interrupt_table[i].id) { 157 return -EALREADY; 158 } 159 } 160 161 type_el3_interrupt_table[index].id = id; 162 type_el3_interrupt_table[index].handler = handler; 163 164 index++; 165 166 return 0; 167 } 168 169 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 170 void *handle, void *cookie) 171 { 172 uint32_t intr_id; 173 uint32_t i; 174 interrupt_type_handler_t handler = NULL; 175 176 intr_id = plat_ic_get_pending_interrupt_id(); 177 178 for (i = 0; i < MAX_INTR_EL3; i++) { 179 if (intr_id == type_el3_interrupt_table[i].id) { 180 handler = type_el3_interrupt_table[i].handler; 181 } 182 } 183 184 if (handler != NULL) { 185 return handler(intr_id, flags, handle, cookie); 186 } 187 188 return 0; 189 } 190 void bl31_platform_setup(void) 191 { 192 /* Initialize the gic cpu and distributor interfaces */ 193 plat_versal_gic_driver_init(); 194 plat_versal_gic_init(); 195 } 196 197 void bl31_plat_runtime_setup(void) 198 { 199 uint64_t flags = 0; 200 int32_t rc; 201 202 set_interrupt_rm_flag(flags, NON_SECURE); 203 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 204 rdo_el3_interrupt_handler, flags); 205 if (rc != 0) { 206 panic(); 207 } 208 } 209 210 /* 211 * Perform the very early platform specific architectural setup here. 212 */ 213 void bl31_plat_arch_setup(void) 214 { 215 plat_arm_interconnect_init(); 216 plat_arm_interconnect_enter_coherency(); 217 218 const mmap_region_t bl_regions[] = { 219 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 220 MT_MEMORY | MT_RW | MT_SECURE), 221 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 222 MT_CODE | MT_SECURE), 223 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 224 MT_RO_DATA | MT_SECURE), 225 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 226 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 227 MT_DEVICE | MT_RW | MT_SECURE), 228 {0} 229 }; 230 231 setup_page_tables(bl_regions, plat_versal_get_mmap()); 232 enable_mmu(0); 233 } 234