1 /* 2 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/dcc.h> 16 #include <drivers/arm/pl011.h> 17 #include <drivers/console.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 #include <plat_arm.h> 22 23 #include <plat_fdt.h> 24 #include <plat_private.h> 25 #include <plat_startup.h> 26 #include "pm_api_sys.h" 27 #include "pm_client.h" 28 #include <pm_ipi.h> 29 #include <versal_def.h> 30 31 static entry_point_info_t bl32_image_ep_info; 32 static entry_point_info_t bl33_image_ep_info; 33 34 /* 35 * Return a pointer to the 'entry_point_info' structure of the next image for 36 * the security state specified. BL33 corresponds to the non-secure image type 37 * while BL32 corresponds to the secure image type. A NULL pointer is returned 38 * if the image does not exist. 39 */ 40 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 41 { 42 assert(sec_state_is_valid(type)); 43 44 if (type == NON_SECURE) { 45 return &bl33_image_ep_info; 46 } 47 48 return &bl32_image_ep_info; 49 } 50 51 /* 52 * Set the build time defaults,if we can't find any config data. 53 */ 54 static inline void bl31_set_default_config(void) 55 { 56 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE; 57 bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr_for_bl32_entry(); 58 bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint(); 59 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 60 DISABLE_ALL_EXCEPTIONS); 61 } 62 63 /* 64 * Perform any BL31 specific platform actions. Here is an opportunity to copy 65 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 66 * are lost (potentially). This needs to be done before the MMU is initialized 67 * so that the memory layout can be used while creating page tables. 68 */ 69 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 70 u_register_t arg2, u_register_t arg3) 71 { 72 uint64_t tfa_handoff_addr; 73 uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE; 74 enum pm_ret_status ret_status; 75 uint64_t addr[HANDOFF_PARAMS_MAX_SIZE]; 76 77 if (VERSAL_CONSOLE_IS(pl011) || (VERSAL_CONSOLE_IS(pl011_1))) { 78 static console_t versal_runtime_console; 79 /* Initialize the console to provide early debug support */ 80 int32_t rc = console_pl011_register((uintptr_t)VERSAL_UART_BASE, 81 (uint32_t)VERSAL_UART_CLOCK, 82 (uint32_t)VERSAL_UART_BAUDRATE, 83 &versal_runtime_console); 84 if (rc == 0) { 85 panic(); 86 } 87 88 console_set_scope(&versal_runtime_console, (uint32_t)(CONSOLE_FLAG_BOOT | 89 CONSOLE_FLAG_RUNTIME)); 90 } else if (VERSAL_CONSOLE_IS(dcc)) { 91 /* Initialize the dcc console for debug */ 92 int32_t rc = console_dcc_register(); 93 if (rc == 0) { 94 panic(); 95 } 96 } else { 97 NOTICE("BL31: Did not register for any console.\n"); 98 } 99 100 /* Initialize the platform config for future decision making */ 101 versal_config_setup(); 102 103 /* Get platform related information */ 104 board_detection(); 105 106 /* 107 * Do initial security configuration to allow DRAM/device access. On 108 * Base VERSAL only DRAM security is programmable (via TrustZone), but 109 * other platforms might have more programmable security devices 110 * present. 111 */ 112 113 /* Populate common information for BL32 and BL33 */ 114 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 115 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 116 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 117 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 118 119 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS, 120 (uintptr_t)addr >> 32U, (uintptr_t)addr, max_size); 121 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); 122 if (ret_status == PM_RET_SUCCESS) { 123 INFO("BL31: GET_HANDOFF_PARAMS call success=%d\n", ret_status); 124 tfa_handoff_addr = (uintptr_t)&addr; 125 } else { 126 ERROR("BL31: GET_HANDOFF_PARAMS Failed, read tfa_handoff_addr from reg\n"); 127 tfa_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4); 128 } 129 130 enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info, 131 &bl33_image_ep_info, 132 tfa_handoff_addr); 133 if (ret == XBL_HANDOFF_NO_STRUCT || ret == XBL_HANDOFF_INVAL_STRUCT) { 134 bl31_set_default_config(); 135 } else if (ret == XBL_HANDOFF_TOO_MANY_PARTS) { 136 ERROR("BL31: Error too many partitions %u\n", ret); 137 } else if (ret != XBL_HANDOFF_SUCCESS) { 138 panic(); 139 } else { 140 INFO("BL31: PLM to TF-A handover success %u\n", ret); 141 } 142 143 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 144 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 145 } 146 147 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 148 149 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 150 { 151 static uint32_t index; 152 uint32_t i; 153 154 /* Validate 'handler' and 'id' parameters */ 155 if (handler == NULL || index >= MAX_INTR_EL3) { 156 return -EINVAL; 157 } 158 159 /* Check if a handler has already been registered */ 160 for (i = 0; i < index; i++) { 161 if (id == type_el3_interrupt_table[i].id) { 162 return -EALREADY; 163 } 164 } 165 166 type_el3_interrupt_table[index].id = id; 167 type_el3_interrupt_table[index].handler = handler; 168 169 index++; 170 171 return 0; 172 } 173 174 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 175 void *handle, void *cookie) 176 { 177 uint32_t intr_id; 178 uint32_t i; 179 interrupt_type_handler_t handler = NULL; 180 181 intr_id = plat_ic_get_pending_interrupt_id(); 182 183 for (i = 0; i < MAX_INTR_EL3; i++) { 184 if (intr_id == type_el3_interrupt_table[i].id) { 185 handler = type_el3_interrupt_table[i].handler; 186 } 187 } 188 189 if (handler != NULL) { 190 return handler(intr_id, flags, handle, cookie); 191 } 192 193 return 0; 194 } 195 196 void bl31_platform_setup(void) 197 { 198 prepare_dtb(); 199 200 /* Initialize the gic cpu and distributor interfaces */ 201 plat_versal_gic_driver_init(); 202 plat_versal_gic_init(); 203 } 204 205 void bl31_plat_runtime_setup(void) 206 { 207 uint64_t flags = 0; 208 int32_t rc; 209 210 set_interrupt_rm_flag(flags, NON_SECURE); 211 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 212 rdo_el3_interrupt_handler, flags); 213 if (rc != 0) { 214 panic(); 215 } 216 } 217 218 /* 219 * Perform the very early platform specific architectural setup here. 220 */ 221 void bl31_plat_arch_setup(void) 222 { 223 plat_arm_interconnect_init(); 224 plat_arm_interconnect_enter_coherency(); 225 226 const mmap_region_t bl_regions[] = { 227 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 228 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 229 MT_MEMORY | MT_RW | MT_NS), 230 #endif 231 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 232 MT_MEMORY | MT_RW | MT_SECURE), 233 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 234 MT_CODE | MT_SECURE), 235 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 236 MT_RO_DATA | MT_SECURE), 237 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 238 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 239 MT_DEVICE | MT_RW | MT_SECURE), 240 {0} 241 }; 242 243 setup_page_tables(bl_regions, plat_versal_get_mmap()); 244 enable_mmu(0); 245 } 246