xref: /rk3399_ARM-atf/plat/xilinx/versal/bl31_versal_setup.c (revision 74464d5b51954b500a1a656539a88a58e70d9b8a)
1 /*
2  * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 #include <errno.h>
9 #include <plat_arm.h>
10 #include <plat_private.h>
11 #include <bl31/bl31.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <drivers/arm/pl011.h>
15 #include <drivers/console.h>
16 #include <lib/xlat_tables/xlat_tables.h>
17 #include <plat/common/platform.h>
18 
19 static entry_point_info_t bl32_image_ep_info;
20 static entry_point_info_t bl33_image_ep_info;
21 static console_pl011_t versal_runtime_console;
22 
23 /*
24  * Return a pointer to the 'entry_point_info' structure of the next image for
25  * the security state specified. BL33 corresponds to the non-secure image type
26  * while BL32 corresponds to the secure image type. A NULL pointer is returned
27  * if the image does not exist.
28  */
29 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
30 {
31 	assert(sec_state_is_valid(type));
32 
33 	if (type == NON_SECURE)
34 		return &bl33_image_ep_info;
35 
36 	return &bl32_image_ep_info;
37 }
38 
39 /*
40  * Perform any BL31 specific platform actions. Here is an opportunity to copy
41  * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
42  * are lost (potentially). This needs to be done before the MMU is initialized
43  * so that the memory layout can be used while creating page tables.
44  */
45 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
46 				u_register_t arg2, u_register_t arg3)
47 {
48 
49 	/* Initialize the console to provide early debug support */
50 	int rc = console_pl011_register(VERSAL_UART_BASE,
51 					VERSAL_UART_CLOCK,
52 					VERSAL_UART_BAUDRATE,
53 					&versal_runtime_console);
54 	if (rc == 0)
55 		panic();
56 
57 	console_set_scope(&versal_runtime_console.console, CONSOLE_FLAG_BOOT |
58 			  CONSOLE_FLAG_RUNTIME);
59 
60 	/* Initialize the platform config for future decision making */
61 	versal_config_setup();
62 	/* There are no parameters from BL2 if BL31 is a reset vector */
63 	assert(arg0 == 0U);
64 	assert(arg1 == 0U);
65 
66 	/*
67 	 * Do initial security configuration to allow DRAM/device access. On
68 	 * Base VERSAL only DRAM security is programmable (via TrustZone), but
69 	 * other platforms might have more programmable security devices
70 	 * present.
71 	 */
72 
73 	/* Populate common information for BL32 and BL33 */
74 	SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
75 	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
76 	SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
77 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
78 
79 	/* use build time defaults in JTAG boot mode */
80 	bl32_image_ep_info.pc = BL32_BASE;
81 	bl32_image_ep_info.spsr = 0;
82 	bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
83 	bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
84 					  DISABLE_ALL_EXCEPTIONS);
85 
86 	NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
87 	NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
88 }
89 
90 void bl31_platform_setup(void)
91 {
92 	/* Initialize the gic cpu and distributor interfaces */
93 	plat_versal_gic_driver_init();
94 	plat_versal_gic_init();
95 }
96 
97 void bl31_plat_runtime_setup(void)
98 {
99 }
100 
101 /*
102  * Perform the very early platform specific architectural setup here.
103  */
104 void bl31_plat_arch_setup(void)
105 {
106 	plat_arm_interconnect_init();
107 	plat_arm_interconnect_enter_coherency();
108 
109 	const mmap_region_t bl_regions[] = {
110 		MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
111 			MT_MEMORY | MT_RW | MT_SECURE),
112 		MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
113 				MT_CODE | MT_SECURE),
114 		MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
115 				MT_RO_DATA | MT_SECURE),
116 		MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
117 				BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
118 				MT_DEVICE | MT_RW | MT_SECURE),
119 		{0}
120 	};
121 
122 	setup_page_tables(bl_regions, plat_versal_get_mmap());
123 	enable_mmu_el3(0);
124 }
125