1 /* 2 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 #include <plat/common/platform.h> 18 #include <plat_arm.h> 19 #include <plat_console.h> 20 21 #include <plat_fdt.h> 22 #include <plat_private.h> 23 #include <plat_startup.h> 24 #include "pm_api_sys.h" 25 #include "pm_client.h" 26 #include <pm_ipi.h> 27 #include <versal_def.h> 28 29 static entry_point_info_t bl32_image_ep_info; 30 static entry_point_info_t bl33_image_ep_info; 31 32 /* 33 * Return a pointer to the 'entry_point_info' structure of the next image for 34 * the security state specified. BL33 corresponds to the non-secure image type 35 * while BL32 corresponds to the secure image type. A NULL pointer is returned 36 * if the image does not exist. 37 */ 38 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 39 { 40 assert(sec_state_is_valid(type)); 41 42 if (type == NON_SECURE) { 43 return &bl33_image_ep_info; 44 } 45 46 return &bl32_image_ep_info; 47 } 48 49 /* 50 * Set the build time defaults,if we can't find any config data. 51 */ 52 static inline void bl31_set_default_config(void) 53 { 54 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE; 55 bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr_for_bl32_entry(); 56 bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint(); 57 bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, 58 DISABLE_ALL_EXCEPTIONS); 59 } 60 61 /* 62 * Perform any BL31 specific platform actions. Here is an opportunity to copy 63 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 64 * are lost (potentially). This needs to be done before the MMU is initialized 65 * so that the memory layout can be used while creating page tables. 66 */ 67 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 68 u_register_t arg2, u_register_t arg3) 69 { 70 uint64_t tfa_handoff_addr; 71 uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE; 72 enum pm_ret_status ret_status; 73 uint64_t addr[HANDOFF_PARAMS_MAX_SIZE]; 74 75 setup_console(); 76 77 /* Initialize the platform config for future decision making */ 78 versal_config_setup(); 79 80 /* Get platform related information */ 81 board_detection(); 82 83 /* 84 * Do initial security configuration to allow DRAM/device access. On 85 * Base VERSAL only DRAM security is programmable (via TrustZone), but 86 * other platforms might have more programmable security devices 87 * present. 88 */ 89 90 /* Populate common information for BL32 and BL33 */ 91 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 92 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 93 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 94 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 95 96 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS, 97 (uintptr_t)addr >> 32U, (uintptr_t)addr, max_size); 98 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); 99 if (ret_status == PM_RET_SUCCESS) { 100 INFO("BL31: GET_HANDOFF_PARAMS call success=%d\n", ret_status); 101 tfa_handoff_addr = (uintptr_t)&addr; 102 } else { 103 ERROR("BL31: GET_HANDOFF_PARAMS Failed, read tfa_handoff_addr from reg\n"); 104 tfa_handoff_addr = mmio_read_32(PMC_GLOBAL_GLOB_GEN_STORAGE4); 105 } 106 107 enum xbl_handoff ret = xbl_handover(&bl32_image_ep_info, 108 &bl33_image_ep_info, 109 tfa_handoff_addr); 110 if (ret == XBL_HANDOFF_NO_STRUCT || ret == XBL_HANDOFF_INVAL_STRUCT) { 111 bl31_set_default_config(); 112 } else if (ret == XBL_HANDOFF_TOO_MANY_PARTS) { 113 ERROR("BL31: Error too many partitions %u\n", ret); 114 } else if (ret != XBL_HANDOFF_SUCCESS) { 115 panic(); 116 } else { 117 INFO("BL31: PLM to TF-A handover success %u\n", ret); 118 } 119 120 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 121 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 122 } 123 124 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 125 126 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 127 { 128 static uint32_t index; 129 uint32_t i; 130 131 /* Validate 'handler' and 'id' parameters */ 132 if (handler == NULL || index >= MAX_INTR_EL3) { 133 return -EINVAL; 134 } 135 136 /* Check if a handler has already been registered */ 137 for (i = 0; i < index; i++) { 138 if (id == type_el3_interrupt_table[i].id) { 139 return -EALREADY; 140 } 141 } 142 143 type_el3_interrupt_table[index].id = id; 144 type_el3_interrupt_table[index].handler = handler; 145 146 index++; 147 148 return 0; 149 } 150 151 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 152 void *handle, void *cookie) 153 { 154 uint32_t intr_id; 155 uint32_t i; 156 interrupt_type_handler_t handler = NULL; 157 158 intr_id = plat_ic_get_pending_interrupt_id(); 159 160 for (i = 0; i < MAX_INTR_EL3; i++) { 161 if (intr_id == type_el3_interrupt_table[i].id) { 162 handler = type_el3_interrupt_table[i].handler; 163 } 164 } 165 166 if (handler != NULL) { 167 return handler(intr_id, flags, handle, cookie); 168 } 169 170 return 0; 171 } 172 173 void bl31_platform_setup(void) 174 { 175 prepare_dtb(); 176 177 /* Initialize the gic cpu and distributor interfaces */ 178 plat_versal_gic_driver_init(); 179 plat_versal_gic_init(); 180 } 181 182 void bl31_plat_runtime_setup(void) 183 { 184 uint64_t flags = 0; 185 int32_t rc; 186 187 set_interrupt_rm_flag(flags, NON_SECURE); 188 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 189 rdo_el3_interrupt_handler, flags); 190 if (rc != 0) { 191 panic(); 192 } 193 } 194 195 /* 196 * Perform the very early platform specific architectural setup here. 197 */ 198 void bl31_plat_arch_setup(void) 199 { 200 plat_arm_interconnect_init(); 201 plat_arm_interconnect_enter_coherency(); 202 203 const mmap_region_t bl_regions[] = { 204 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE) && \ 205 (!defined(PLAT_XLAT_TABLES_DYNAMIC))) 206 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 207 MT_MEMORY | MT_RW | MT_NS), 208 #endif 209 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 210 MT_MEMORY | MT_RW | MT_SECURE), 211 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 212 MT_CODE | MT_SECURE), 213 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 214 MT_RO_DATA | MT_SECURE), 215 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 216 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 217 MT_DEVICE | MT_RW | MT_SECURE), 218 {0} 219 }; 220 221 setup_page_tables(bl_regions, plat_versal_get_mmap()); 222 enable_mmu(0); 223 } 224